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* Fix indent in comment.Nick Lewycky2011-10-121-1/+1
| | | | llvm-svn: 141749
* Fix r141744.Evan Cheng2011-10-121-1/+19
| | | | | | | | | 1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. llvm-svn: 141747
* Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen2011-10-121-3/+29
| | | | | | | | | | | | | | | | | | | | | | When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. llvm-svn: 141746
* Refine r141689 with a tri-state variable.Evan Cheng2011-10-111-19/+23
| | | | | | Also teach MachineLICM to avoid "speculation" when register pressure is high. llvm-svn: 141744
* Change name of class to ArithOverflowR.Akira Hatanaka2011-10-111-3/+3
| | | | llvm-svn: 141743
* Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logicalAkira Hatanaka2011-10-112-35/+19
| | | | | | instructions with two register operands derive from it. llvm-svn: 141742
* Fix comment.Akira Hatanaka2011-10-111-1/+1
| | | | llvm-svn: 141737
* Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bitAkira Hatanaka2011-10-112-43/+25
| | | | | | | arithmetic and logical instructions with three register operands derive from them. Fix instruction encoding too. llvm-svn: 141736
* Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher2011-10-114-4/+64
| | | | | | | | | | | | | file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 llvm-svn: 141729
* Formatting.Eric Christopher2011-10-111-2/+1
| | | | llvm-svn: 141728
* Spacing.Eric Christopher2011-10-111-1/+1
| | | | llvm-svn: 141727
* N.B. This is with the new EH scheme:Bill Wendling2011-10-111-0/+5
| | | | | | | | | | | | | | | The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. llvm-svn: 141726
* Fix function isUnalignedLoadStore.Akira Hatanaka2011-10-111-2/+4
| | | | llvm-svn: 141722
* ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.Jim Grosbach2011-10-112-64/+139
| | | | | | | | Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
* Remove unused PatLeaf.Akira Hatanaka2011-10-111-4/+0
| | | | llvm-svn: 141720
* Change the names of 64-bit logical instructions so that they match the names ofAkira Hatanaka2011-10-111-8/+8
| | | | | | the real instructions. llvm-svn: 141718
* Revert r141529. This is causing failures in the test-suite, like bigstack ↵Bill Wendling2011-10-111-11/+2
| | | | | | and ReedSolomon. Boo... llvm-svn: 141716
* Remove redundancy in setcc patterns using multiclass.Akira Hatanaka2011-10-112-48/+47
| | | | llvm-svn: 141715
* Fix PR11106 by correcting a typo that has been in the code for over a year. ThisCameron Zwarich2011-10-111-2/+2
| | | | | | | | would have never worked, since the element type of a vector type is never a vector type. Also fix the conditional to be more direct in checking whether EltTy is a vector type. llvm-svn: 141713
* Use sltiu instead of sltu when a register operand and immediate are compared.Akira Hatanaka2011-10-112-2/+2
| | | | llvm-svn: 141708
* ARM addressing mode cleanup for LDC/STC.Jim Grosbach2011-10-111-16/+20
| | | | | | | We parse at least some forms of the instructions now. Encoding is pretty screwed up, still, though. llvm-svn: 141704
* Clean up a few references to System/. We still have docs/SystemLibrary.htmlDaniel Dunbar2011-10-115-5/+5
| | | | | | lying around... llvm-svn: 141703
* Add patterns for conditional branches with 64-bit register operands.Akira Hatanaka2011-10-112-21/+30
| | | | llvm-svn: 141696
* Add support for 64-bit set-on-less-than instructions.Akira Hatanaka2011-10-112-14/+44
| | | | llvm-svn: 141695
* Add support for conditional branch instructions with 64-bit register operands.Akira Hatanaka2011-10-114-34/+67
| | | | llvm-svn: 141694
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-111-1/+46
| | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141689
* Expose MachOObjectFile externally, like we do for COFF. First step in ↵Owen Anderson2011-10-111-80/+3
| | | | | | reducing the amount of special-purpose code needed for llvm-objdump. llvm-svn: 141684
* ARM parse alignment specifier for NEON load/store instructions.Jim Grosbach2011-10-112-29/+93
| | | | llvm-svn: 141682
* ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.Jim Grosbach2011-10-111-113/+113
| | | | llvm-svn: 141671
* Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem2011-10-111-0/+25
| | | | llvm-svn: 141667
* Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.Richard Osborne2011-10-113-6/+64
| | | | | | | This fixes an assert due to the operands of the DBG_VALUE instruction not being as expected (PR11105). llvm-svn: 141666
* Fix a iterator out of bounds error, that triggers rarely.Kalle Raiskila2011-10-111-0/+2
| | | | llvm-svn: 141665
* Add support for legalization of vector trunc-store where the saved scalar ↵Nadav Rotem2011-10-111-13/+13
| | | | | | type is illegal (for example, v2i16 on systems where the smallest store size is i32) llvm-svn: 141661
* Cleanup the trunc-store legalization code and add asserts.Nadav Rotem2011-10-111-68/+87
| | | | llvm-svn: 141659
* Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as ↵Craig Topper2011-10-112-20/+23
| | | | | | modifying EFLAGS. llvm-svn: 141656
* Make Ivy Bridge 16-bit floating point conversion instructions require AVX.Craig Topper2011-10-111-1/+1
| | | | llvm-svn: 141654
* Add X86 LZCNT instruction. Including instruction selection support.Craig Topper2011-10-115-7/+50
| | | | llvm-svn: 141651
* Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc'sCameron Zwarich2011-10-111-205/+16
| | | | | | | lowering of NEON code. It provides little-to-no benefit now and only introduces additional complexity. llvm-svn: 141646
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-112-68/+3
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Also create a shndx even if there are no symbols. This lets us testNick Lewycky2011-10-111-0/+3
| | | | | | | .symtab_shndx reading and writing together, and finally we have a testcase for r141440. llvm-svn: 141641
* Reapply r141605 with fixes for appropriate handling of reserved section numbersNick Lewycky2011-10-111-17/+50
| | | | | | in st_shndx fields. llvm-svn: 141639
* Add support for .symtab_shnidx. Unfortunately, doing this required breaking aNick Lewycky2011-10-111-9/+42
| | | | | | | layer of abstraction around SymbolRef where you can read its private SymbolPimpl member. llvm-svn: 141636
* Add experimental -enable-lsr-phielim option.Andrew Trick2011-10-111-0/+22
| | | | | | | I'm not sure we will need it in the long run, but the option is currently useful for checking if the output of LSR is "clean". llvm-svn: 141634
* Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"Andrew Trick2011-10-112-87/+106
| | | | | | | | | | | IVs. Indvars previously chose randomly between congruent IVs. Now it will bias the decision toward IVs that SCEVExpander likes to create. This was not done to fix any problem, it's just a welcome side effect of factoring code. llvm-svn: 141633
* Make changes necessary for supporting floating point load and store instructionsAkira Hatanaka2011-10-114-23/+50
| | | | | | | that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. llvm-svn: 141623
* Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().Jakob Stoklund Olesen2011-10-112-30/+44
| | | | | | | | | | | The VMOVS widening needs to look at the implicit COPY operands. Trying to dig out the COPY instruction from an iterator in copyPhysReg() is the wrong approach. The expandPostRAPseudo() hook gets to look at COPY instructions before they are converted to copyPhysReg() calls. llvm-svn: 141619
* Modify lowering of GlobalAddress so that correct code is emitted when target isAkira Hatanaka2011-10-113-14/+23
| | | | | | Mips64. llvm-svn: 141618
* Fixed natural stack alignment for Linux x86-32. Thanks Eli.Lang Hames2011-10-111-1/+1
| | | | llvm-svn: 141616
* Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.Akira Hatanaka2011-10-111-7/+10
| | | | llvm-svn: 141615
* Revert r141605 as it broke tests for llvm-nm.Nick Lewycky2011-10-111-34/+13
| | | | llvm-svn: 141614
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