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authorAkira Hatanaka <ahatanaka@mips.com>2011-10-11 23:43:48 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-10-11 23:43:48 +0000
commit0f4ecf75486973a0c0eda5b07b3eb1895a0bb364 (patch)
treead6416a711fc5a8acfa5c1d5f62eca50b9316127 /llvm/lib
parent8f0d549c4c6bc9d05745016ec2a85e1ee45652e5 (diff)
downloadbcm5719-llvm-0f4ecf75486973a0c0eda5b07b3eb1895a0bb364.tar.gz
bcm5719-llvm-0f4ecf75486973a0c0eda5b07b3eb1895a0bb364.zip
Change name of class to ArithOverflowR.
llvm-svn: 141743
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 4938cf8bc94..2ee32fa540a 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -260,7 +260,7 @@ class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
let isCommutable = isComm;
}
-class ArithLogicOfR<bits<6> op, bits<6> func, string instr_asm,
+class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
@@ -616,8 +616,8 @@ def LUi : LoadUpper<0x0f, "lui">;
/// Arithmetic Instructions (3-Operand, R-Type)
def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
-def ADD : ArithLogicOfR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
-def SUB : ArithLogicOfR<0x00, 0x22, "sub", IIAlu, CPURegs>;
+def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
+def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
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