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* Use iPTR instead of i32 for extract_subvector/insert_subvector index in ↵Craig Topper2012-09-062-78/+78
| | | | | | lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. llvm-svn: 163293
* Add patterns for converting stores of subvector_extracts of lower 128-bits ↵Craig Topper2012-09-061-0/+40
| | | | | | of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. llvm-svn: 163292
* Whitespace.NAKAMURA Takumi2012-09-061-2/+2
| | | | llvm-svn: 163289
* Unix/Signals.inc: Fix a typo. Thanks to Dani Berg!NAKAMURA Takumi2012-09-061-1/+1
| | | | llvm-svn: 163288
* There are some Mips instructions that are lowered by the Jack Carter2012-09-066-95/+124
| | | | | | | | | | | | | | | | assembler such as shifts greater than 32. In the case of direct object, the code gen needs to do this lowering since the assembler is not involved. With the advent of the llvm-mc assembler, it also needs to do the same lowering. This patch makes that specific lowering code accessible to both the direct object output and the assembler. This patch does not affect generated output. llvm-svn: 163287
* Update function names to conform to guidelines.Jim Grosbach2012-09-061-26/+26
| | | | | | No functional change. llvm-svn: 163279
* Mips specific llvm assembler support for branch and jump instructions.Jack Carter2012-09-061-2/+9
| | | | | | | Test case included. Contributer: Vladimir Medic llvm-svn: 163277
* Remove predicated pseudo-instructions.Jakob Stoklund Olesen2012-09-052-100/+0
| | | | | | | These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. llvm-svn: 163275
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-051-56/+31
| | | | | | | | | | | | | | | | | | | | Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
* [ms-inline asm] Use the asm dialect from the MI to set the parser dialect.Chad Rosier2012-09-051-2/+4
| | | | llvm-svn: 163273
* JumpThreading: when default destination is the destination of some cases in aManman Ren2012-09-051-3/+6
| | | | | | | | | switch, make sure we include the value for the cases when calculating edge value from switch to the default destination. rdar://12241132 llvm-svn: 163270
* Mips specific llvm assembler support for ALU instructions. This includesJack Carter2012-09-051-22/+367
| | | | | | | register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
* Cleanup a few magic numbers.Chad Rosier2012-09-052-2/+2
| | | | llvm-svn: 163263
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-0514-17/+17
| | | | llvm-svn: 163258
* [ms-inline asm] We only need one bit to represent the AsmDialect in theChad Rosier2012-09-052-11/+5
| | | | | | MachineInstr. llvm-svn: 163257
* Constify this properly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-051-4/+4
| | | | llvm-svn: 163256
* Mark checkSignature const, and in turn stop casting away const fromRoman Divacky2012-09-052-3/+3
| | | | | | ArchiveMemberHeader. Found by gcc48 -Wcast-qual. llvm-svn: 163255
* Constify SDNodeIterator an stop its only non-const user being cast strippedRoman Divacky2012-09-051-1/+1
| | | | | | of its constness. Found by gcc48 -Wcast-qual. llvm-svn: 163254
* Constify subtarget info properly so that we dont cast away the const inRoman Divacky2012-09-052-6/+6
| | | | | | the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. llvm-svn: 163251
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-053-13/+13
| | | | | | by casting. Found with gcc48. llvm-svn: 163247
* [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.Chad Rosier2012-09-052-1/+19
| | | | llvm-svn: 163243
* Move the PPC TOC defs into the PPC64 InstrInfo file.Hal Finkel2012-09-052-3/+3
| | | | | | | | Since TOC is just defined for PPC64, move its definition to PPC64 td file. Patch by Adhemerval Zanella. llvm-svn: 163234
* [ms-inline asm] Enumerate the InlineAsm dialects and rename the nsdialect toChad Rosier2012-09-058-17/+19
| | | | | | inteldialect. llvm-svn: 163231
* Strip old MachineInstrs *after* we know we can put them back.Tim Northover2012-09-051-6/+6
| | | | | | | | Previous patch accidentally decided it couldn't convert a VFP to a NEON instruction after it had already destroyed the old one. Not a good move. llvm-svn: 163230
* Remove unused typedefs gcc4.8 warns about.Roman Divacky2012-09-052-2/+0
| | | | llvm-svn: 163225
* MCJIT: getPointerToFunction() references target address space.Jim Grosbach2012-09-053-2/+27
| | | | | | | Make sure to return a pointer into the target memory, not the local memory. Often they are the same, but we can't assume that. llvm-svn: 163217
* Switch BasicAliasAnalysis' cache to SmallDenseMap.Benjamin Kramer2012-09-051-9/+7
| | | | | | | | It relies on clear() being fast and the cache rarely has more than 1 or 2 elements, so give it an inline capacity and always shrink it back down in case it grows. DenseMap will grow to 64 buckets which makes clear() a lot slower. llvm-svn: 163215
* LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access thePranav Bhandarkar2012-09-051-0/+35
| | | | | | | | | | | | | | | subreg_hireg of register pair Rp. * lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New DenseMap similar to PeepholeMap that additionally records subreg info too. (runOnMachineFunction): Record information in PeepholeDoubleRegsMap and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to the instruction Rx = COPY Rp1:logreg_subreg. * test/CodeGen/Hexagon/remove_lsr.ll: New test. llvm-svn: 163214
* [asan] fix lintKostya Serebryany2012-09-051-1/+1
| | | | llvm-svn: 163205
* Fixed the DAG combiner to better handle the folding of AND nodes for vector ↵Silviu Baranga2012-09-051-1/+11
| | | | | | types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. llvm-svn: 163203
* [asan] extend the blacklist functionality to handle global-init. Patch by ↵Kostya Serebryany2012-09-053-1/+11
| | | | | | Reid Watson llvm-svn: 163199
* Remove some of the patterns added in r163196. Increasing the complexity on ↵Craig Topper2012-09-051-42/+2
| | | | | | insert_subvector into undef accomplishes the same thing. llvm-svn: 163198
* Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. ↵Craig Topper2012-09-051-4/+76
| | | | | | Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS. llvm-svn: 163196
* Add a FIXME that assumes we maintain backward compatibility until the next ↵Chad Rosier2012-09-051-0/+1
| | | | | | major release. llvm-svn: 163195
* Reorder the comments of EmitExceptionTable.Logan Chien2012-09-051-20/+20
| | | | llvm-svn: 163194
* Fix UseInitArray option for MIPS target.Logan Chien2012-09-051-0/+1
| | | | llvm-svn: 163193
* Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG ↵Craig Topper2012-09-052-29/+66
| | | | | | build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. llvm-svn: 163192
* Remove redundant semicolons to fix -pedantic-errors build.Richard Smith2012-09-051-2/+2
| | | | llvm-svn: 163190
* Fix function name per coding standard.Chad Rosier2012-09-054-10/+10
| | | | llvm-svn: 163187
* [ms-inline asm] Add support for the nsdialect keyword in the BitcodeChad Rosier2012-09-052-2/+28
| | | | | | Reader/Writer. llvm-svn: 163185
* [ms-inline asm] Add the nsdialect keyword to the lexer.Chad Rosier2012-09-051-0/+1
| | | | llvm-svn: 163184
* [ms-inline asm] Emit the (new) inline asm Non-Standard Dialect attribute.Chad Rosier2012-09-053-3/+9
| | | | llvm-svn: 163181
* Make provenance checking conservative in cases whenDan Gohman2012-09-041-37/+42
| | | | | | | | pointers-to-strong-pointers may be in play. These can lead to retains and releases happening in unstructured ways, foiling the optimizer. This fixes rdar://12150909. llvm-svn: 163180
* BypassSlowDivision: Assign to reference, don't copy the object.Jakub Staszak2012-09-041-2/+2
| | | | llvm-svn: 163179
* Search the whole instruction for tied operands.Jakob Stoklund Olesen2012-09-041-2/+1
| | | | | | | Implicit uses can be dynamically tied to defs. This will soon be used for predicated instructions on ARM. llvm-svn: 163177
* [ms-inline asm] Add the inline assembly dialect, AsmDialect, to the InlineAsmChad Rosier2012-09-043-13/+23
| | | | | | class. llvm-svn: 163175
* [ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. ThisChad Rosier2012-09-044-6/+0
| | | | | | | implementation does not co-exist well with how the sideeffect and alignstack attributes are handled. The reverts r161641. llvm-svn: 163174
* Fix my previous patch (r163164). It does now what it is supposed to do:Jakub Staszak2012-09-041-1/+0
| | | | | | Doesn't set MadeChange to TRUE if BypassSlowDivision doesn't change anything. llvm-svn: 163165
* Return false if BypassSlowDivision doesn't change anything.Jakub Staszak2012-09-041-33/+34
| | | | | | | | | | Also a few minor changes: - use pre-inc instead of post-inc - use isa instead of dyn_cast - 80 col - trailing spaces llvm-svn: 163164
* Typo.Jakob Stoklund Olesen2012-09-041-1/+1
| | | | llvm-svn: 163154
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