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* [AMDGPU] Drop Reg32 and use regular AsmNameStanislav Mekhanoshin2019-07-183-25/+21
| | | | | | | | This allows to reduce generated AMDGPUGenAsmWriter.inc by ~100Kb. Differential Revision: https://reviews.llvm.org/D64952 llvm-svn: 366505
* [GlobalISel][AArch64] Add support for base register + offset register loadsJessica Paquette2019-07-181-0/+93
| | | | | | | | | | | | | | | | | | | | Add support for folding G_GEPs into loads of the form ``` ldr reg, [base, off] ``` when possible. This can save an add before the load. Currently, this is only supported for loads of 64 bits into 64 bit registers. Add a new addressing mode function, `selectAddrModeRegisterOffset` which performs this folding when it is profitable. Also add a test for addressing modes for G_LOAD. Differential Revision: https://reviews.llvm.org/D64944 llvm-svn: 366503
* CodeGen: Allow !associated metadata to point to aliases.Peter Collingbourne2019-07-181-2/+2
| | | | | | | | | | This is a small extension of !associated, mostly useful for the implementation convenience of instrumentation passes that RAUW globals with aliases, such as LowerTypeTests. Differential Revision: https://reviews.llvm.org/D64951 llvm-svn: 366502
* Revert [X86] EltsFromConsecutiveLoads - support common source loadsReid Kleckner2019-07-181-63/+5
| | | | | | | | This reverts r366441 (git commit 48104ef7c9c653bbb732b66d7254957389fea337) This causes clang to fail to compile some file in Skia. Reduction soon. llvm-svn: 366501
* [WebAssembly] Fix __builtin_wasm_tls_base intrinsicGuanzhong Chen2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Properly generate the outchain for the `__builtin_wasm_tls_base` intrinsic. Also marked the intrinsic pure, per @sunfish's suggestion. Reviewers: tlively, aheejin, sbc100, sunfish Reviewed By: tlively Subscribers: dschuff, jgravelle-google, hiraditya, cfe-commits, llvm-commits, sunfish Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D64949 llvm-svn: 366499
* Fix typo in r366494. Spotted by Yuanfang Chen.Peter Collingbourne2019-07-181-1/+1
| | | | llvm-svn: 366497
* Remove the static initialize introduced in r365099Steven Wu2019-07-181-9/+11
| | | | | | | | | | | | | | | | | | Summary: Some polish for r365099 which adds a static initializer to MachOObjectFile. Remove it by moving it to file scope. Reviewers: smeenai, alexshap, compnerd, mtrent, anushabasana Reviewed By: smeenai Subscribers: hiraditya, jkorous, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64873 llvm-svn: 366496
* IR: Teach Constant::needsRelocation() that relative pointers don't need to ↵Peter Collingbourne2019-07-181-11/+23
| | | | | | | | | | | be relocated. This causes sections with relative pointers to be marked as read only, which means that they won't end up sharing pages with writable data. Differential Revision: https://reviews.llvm.org/D64948 llvm-svn: 366494
* FileSystem: Check for DTTOIF alone, not _DIRENT_HAVE_D_TYPEJordan Rose2019-07-181-1/+4
| | | | | | | | | | | | | | | | | | | | | | | While 'd_type' is a non-standard extension to `struct dirent`, only glibc signals its presence with a macro '_DIRENT_HAVE_D_TYPE'. However, any platform with 'd_type' also includes a way to convert to mode_t values using the macro 'DTTOIF', so we can check for that alone and still be confident that the 'd_type' member exists. (If this turns out to be wrong, I'll go back and set up an actual CMake check.) I couldn't think of how to write a test for this, because I couldn't think of how to test that a 'stat' call doesn't happen without controlling the filesystem or intercepting 'stat', and there's no good cross-platform way to do that that I know of. Follow-up (almost a year later) to r342089. rdar://problem/50592673 https://reviews.llvm.org/D64940 llvm-svn: 366486
* [ORC] Suppress an ORCv1 deprecation warning.Lang Hames2019-07-181-1/+2
| | | | llvm-svn: 366485
* [COFF] Change a variable type to be const in the HeapAllocSite map.Amy Huang2019-07-184-5/+7
| | | | llvm-svn: 366479
* [WebAssembly] Implement __builtin_wasm_tls_base intrinsicGuanzhong Chen2019-07-181-0/+17
| | | | | | | | | | | | | | | | Summary: Add `__builtin_wasm_tls_base` so that LeakSanitizer can find the thread-local block and scan through it for memory leaks. Reviewers: tlively, aheejin, sbc100 Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D64900 llvm-svn: 366475
* [LAA] Re-check bit-width of pointers after stripping.Michael Liao2019-07-181-1/+14
| | | | | | | | | | | | | | | | Summary: - As the pointer stripping now tracks through `addrspacecast`, prepare to handle the bit-width difference from the result pointer. Reviewers: jdoerfert Subscribers: jvesely, nhaehnle, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64928 llvm-svn: 366470
* MC: AArch64: Add support for prel_g* relocation specifiers.Peter Collingbourne2019-07-184-10/+49
| | | | | | Differential Revision: https://reviews.llvm.org/D64683 llvm-svn: 366462
* AArch64: Unify relocation restrictions between MOVK/MOVN/MOVZ.Peter Collingbourne2019-07-183-104/+51
| | | | | | | | | | | | | | | | | | | | | | | There doesn't seem to be a practical reason for these instructions to have different restrictions on the types of relocations that they may be used with, notwithstanding the language in the ELF AArch64 spec that implies that specific relocations are meant to be used with specific instructions. For example, we currently forbid the first instruction in the following sequence, despite it currently being used by clang to generate a global reference under -mcmodel=large: movz x0, #:abs_g0_nc:foo movk x0, #:abs_g1_nc:foo movk x0, #:abs_g2_nc:foo movk x0, #:abs_g3:foo Therefore, allow MOVK/MOVN/MOVZ to accept the union of the set of relocations that they currently accept individually. Differential Revision: https://reviews.llvm.org/D64466 llvm-svn: 366461
* Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."Hsiangkai Wang2019-07-188-99/+38
| | | | | | This reverts commit 17e3cbf5fe656483d9016d0ba9e1d0cd8629379e. llvm-svn: 366444
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-188-38/+99
| | | | | | | | | | | | | It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366442
* [X86] EltsFromConsecutiveLoads - support common source loadsSimon Pilgrim2019-07-181-5/+63
| | | | | | | | | | | | This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load. A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match. Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle. Differential Revision: https://reviews.llvm.org/D64551 llvm-svn: 366441
* [DAGCombine] Pull getSubVectorSrc helper out of ↵Simon Pilgrim2019-07-181-22/+22
| | | | | | | | narrowInsertExtractVectorBinOp. NFCI. NFC step towards reusing this in other EXTRACT_SUBVECTOR combines. llvm-svn: 366435
* [FileCheck] Fix numeric variable redefinitionThomas Preud'homme2019-07-181-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Commit r365249 changed usage of FileCheckNumericVariable to have one instance of that class per variable as opposed to one instance per definition of a given variable as was done before. However, it retained the safety check in setValue that it should only be called with the variable unset, even after r365625. However this causes assert failure when a non-pseudo variable is being redefined. And while redefinition of @LINE at each CHECK line work in the general case, it caused problem when a substitution failed (fixed in r365624) and still causes problem when a CHECK line does not match since @LINE's value is cleared after substitutions in match() happened but printSubstitutions also attempts a substitution. This commit solves the root of the problem by changing setValue to set a new value regardless of whether a value was set or not, thus fixing all the aforementioned issues. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield Tags: #llvm Differential Revision: https://reviews.llvm.org/D64882 llvm-svn: 366434
* [x86] try harder to form LEA from ADD to avoid flag conflicts (PR40483)Sanjay Patel2019-07-181-0/+31
| | | | | | | | | | | | | | | | LEA doesn't affect flags, so use it more liberally to replace an ADD when we know that the ADD operands affect flags. In the motivating example from PR40483: https://bugs.llvm.org/show_bug.cgi?id=40483 ...this lets us avoid duplicating a math op just to avoid flag conflict. As mentioned in the TODO comments, this heuristic can be extended to fire more often if that leads to more improvements. Differential Revision: https://reviews.llvm.org/D64707 llvm-svn: 366431
* [ARM][DAGCOMBINE][FIX] PerformVMOVRRDCombineDiogo N. Sampaio2019-07-181-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: PerformVMOVRRDCombine ommits adding a offset of 4 to the PointerInfo, when converting a f64 = load[M] to {i32, i32} = {load[M], load[M + 4]} Which would allow the machine scheduller to break dependencies with the second load. - pr42638 Reviewers: eli.friedman, dmgreen, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64870 llvm-svn: 366423
* [SCEV] add no wrap flag for SCEVAddExpr.Chen Zheng2019-07-181-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D64868 llvm-svn: 366419
* [RISCV] Reset NoPHIS MachineFunctionProperty in emitSelectPseudoAlex Bradbury2019-07-181-0/+1
| | | | | | | We insered PHIS were there were none before, so the property must be reset. This error was found on an EXPENSIVE_CHECKS build. llvm-svn: 366412
* [LoopInfo] Use early return in branch weight update functions. NFC.Serguei Katkov2019-07-181-29/+30
| | | | llvm-svn: 366411
* [X86] Disable combineConcatVectors for vXi1 vectors.Craig Topper2019-07-181-0/+4
| | | | | | | | | | | I'm not convinced the code this calls is properly vetted for vXi1 vectors. Experimental vector widening legalization testing for D55251 is now hitting an assertion failure inside EltsFromConsecutiveLoads. This is occurring from a v2i1 load having a store size different than its VT size. Hopefully this commit will keep such issues from happening. llvm-svn: 366405
* [DWARF][RISCV] Add support for RISC-V relocations needed for debug infoAlex Bradbury2019-07-187-11/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When code relaxation is enabled many RISC-V fixups are not resolved but instead relocations are emitted. This happens even for DWARF debug sections. Therefore, to properly support the parsing of DWARF debug info we need to be able to resolve RISC-V relocations. This patch adds: * Support for RISC-V relocations in RelocationResolver * DWARF support for two relocations per object file offset * DWARF changes to support relocations in more DIE fields The two relocations per offset change is needed because some RISC-V relocations (used for label differences) come in pairs. Relocations can also be emitted for DWARF fields where relocations were not yet evaluated. Adding relocation support for some of these fields is essencial. On the other hand, LLVM currently emits RISC-V relocations for fixups that could be safely evaluated, since they can never be affected by code relaxations. This patch also adds relocation support for the fields affected by those extraneous relocations (the DWARF unit entry Length, and the DWARF debug line entry TotalLength and PrologueLength), for testing purposes. Differential Revision: https://reviews.llvm.org/D62062 Patch by Luís Marques. llvm-svn: 366402
* [RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeqAlex Bradbury2019-07-181-1/+1
| | | | | | Found by UBSan. llvm-svn: 366398
* [RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranchAlex Bradbury2019-07-181-2/+2
| | | | | | Issue found by ASan. llvm-svn: 366397
* [AArch64] Add dependency from AArch64CodeGen to TransformUtils to fix ↵Fangrui Song2019-07-181-1/+1
| | | | | | | | | | | -DBUILD_SHARED_LIBS=on link error after D64173/r366361 This fixes: ld.lld: error: undefined symbol: llvm::findAllocaForValue(llvm::Value*, llvm::DenseMap<llvm::Value*, llvm::Alloc aInst*, llvm::DenseMapInfo<llvm::Value*>, llvm::detail::DenseMapPair<llvm::Value*, llvm::AllocaInst*> >&) >>> referenced by AArch64StackTagging.cpp llvm-svn: 366396
* Changes to display code view debug info type records in hex formatNilanjana Basu2019-07-174-7/+19
| | | | llvm-svn: 366390
* Make DT a transitive dependency of LI.Evgeniy Stepanov2019-07-171-1/+1
| | | | | | | | | | | | | | | | | | Summary: LoopInfoWrapperPass::verify uses DT, which means DT must be alive even if it has no direct users. Fixes a crash in expensive checks mode. Reviewers: pcc, leonardchan Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64896 llvm-svn: 366388
* [llvm-bcanalyzer] Fixed error 'Expected<T> must be checked before access or ↵Denis Bakhvalov2019-07-171-2/+5
| | | | | | | | | | | | | | | | destruction' After rL365286 I had failing test: LLVM :: tools/gold/X86/v1.12/thinlto_emit_linked_objects.ll It was failing with the output: $ llvm-bcanalyzer --dump llvm/test/tools/gold/X86/v1.12/Output/thinlto_emit_linked_objects.ll.tmp3.o.thinlto.bc Expected<T> must be checked before access or destruction. Unchecked Expected<T> contained error: Unexpected end of file reading 0 of 0 bytesStack dump: Change-Id: I07e03262074ea5e0aae7a8d787d5487c87f914a2 llvm-svn: 366387
* llvm-pdbdump: Fix several smaller issues with injected source compression ↵Nico Weber2019-07-173-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | handling - getCompression() used to return a PDB_SourceCompression even though the docs for IDiaInjectedSource are explicit about the return value being compiler-dependent. Return an uint32_t instead, and make the printing code handle unknown values better by printing "Unknown" and the int value instead of not printing any compression. - Print compressed contents as hex dump, not as string. - Add compression type "DotNet", which is used (at least) by csc.exe, the C# compiler. Also add a lengthy comment describing the stream contents (derived from looking at the raw hex contents long enough to see the GUIDs, which led me to the roslyn and mono implementations for handling this). - The native injected source dumper was dumping the contents of the whole data stream -- but csc.exe writes a stream that's padded with zero bytes to the next 512 boundary, and the dia api doesn't display those padding bytes. So make NativeInjectedSource::getCode() do the same thing. Differential Revision: https://reviews.llvm.org/D64879 llvm-svn: 366386
* [AMDGPU] Simplify AMDGPUInstPrinter::printRegOperand()Stanislav Mekhanoshin2019-07-172-157/+37
| | | | | | Differential Revision: https://reviews.llvm.org/D64892 llvm-svn: 366385
* [X86] Make sure we mark 128/256 MLOAD as Legal with VLX when ↵Craig Topper2019-07-171-5/+7
| | | | | | | | | min-legal-vector-width=256 is in effect. This started triggering an assertion after r364718 when we made these Custom under AVX2. llvm-svn: 366382
* hwasan: Initialize the pass only once.Peter Collingbourne2019-07-172-8/+21
| | | | | | | | | | This will let us instrument globals during initialization. This required making the new PM pass a module pass, which should still provide access to analyses via the ModuleAnalysisManager. Differential Revision: https://reviews.llvm.org/D64843 llvm-svn: 366379
* [AMDGPU] Stop special casing flat_scratch for register nameStanislav Mekhanoshin2019-07-172-13/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D64885 llvm-svn: 366376
* Speculative fix for stack-tagging.ll failure.Evgeniy Stepanov2019-07-171-2/+2
| | | | | | | Depending on the evaluation order of function call arguments, the current code may insert a use before def. llvm-svn: 366375
* [Attributor][NFC] Remove unnecessary debug outputHideto Ueno2019-07-171-1/+0
| | | | llvm-svn: 366373
* Adding inline comments to code view type record directives for better ↵Nilanjana Basu2019-07-173-127/+172
| | | | | | readability llvm-svn: 366372
* [PEI] Don't re-allocate a pre-allocated stack protector slotFrancis Visoiu Mistrih2019-07-172-2/+27
| | | | | | | | | | | | | | | | | | | | | | The LocalStackSlotPass pre-allocates a stack protector and makes sure that it comes before the local variables on the stack. We need to make sure that later during PEI we don't re-allocate a new stack protector slot. If that happens, the new stack protector slot will end up being **after** the local variables that it should be protecting. Therefore, we would have two slots assigned for two different stack protectors, one at the top of the stack, and one at the bottom. Since PEI will overwrite the assigned slot for the stack protector, the load that is used to compare the value of the stack protector will use the slot assigned by PEI, which is wrong. For this, we need to check if the object is pre-allocated, and re-use that pre-allocated slot. Differential Revision: https://reviews.llvm.org/D64757 llvm-svn: 366371
* [CodeGen][NFC] Simplify checks for stack protector index checkingFrancis Visoiu Mistrih2019-07-172-13/+11
| | | | | | | Use `hasStackProtectorIndex()` instead of `getStackProtectorIndex() >= 0`. llvm-svn: 366369
* GlobalISel: Handle widenScalar of arbitrary G_MERGE_VALUES sourcesMatt Arsenault2019-07-172-48/+87
| | | | | | | | | | | Extract the sources to the GCD of the original size and target size, padding with implicit_def as necessary. Also fix the case where the requested source type is wider than the original result type. This was ignoring the type, and just using the destination. Do the operation in the requested type and truncate back. llvm-svn: 366367
* GlobalISel: Handle more cases for widenScalar of G_MERGE_VALUESMatt Arsenault2019-07-171-4/+23
| | | | | | | | | | | | Use an anyext to the requested type for the leftover operand to produce a slightly wider type, and then truncate the final merge. I have another implementation almost ready which handles arbitrary widens, but I think it produces worse code in this example (which I think is 90% due to not folding redundant copies or folding out implicit_def users), so I wanted to add this as a baseline first. llvm-svn: 366366
* Basic MTE stack tagging instrumentation.Evgeniy Stepanov2019-07-174-0/+351
| | | | | | | | | | | | | | | | Summary: Use MTE intrinsics to tag stack variables in functions with sanitize_memtag attribute. Reviewers: pcc, vitalybuka, hctim, ostannard Subscribers: srhines, mgorny, javed.absar, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64173 llvm-svn: 366361
* Basic codegen for MTE stack tagging.Evgeniy Stepanov2019-07-1714-8/+372
| | | | | | | | | | | | Implement IR intrinsics for stack tagging. Generated code is very unoptimized for now. Two special intrinsics, llvm.aarch64.irg.sp and llvm.aarch64.tagp are used to implement a tagged stack frame pointer in a virtual register. Differential Revision: https://reviews.llvm.org/D64172 llvm-svn: 366360
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-174-77/+12
| | | | | | This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) llvm-svn: 366355
* [AMDGPU] Tune inlining parameters for AMDGPU targetDaniil Fukalov2019-07-174-12/+9
| | | | | | | | | | | | | | | | | | | Summary: Since the target has no significant advantage of vectorization, vector instructions bous threshold bonus should be optional. amdgpu-inline-arg-alloca-cost parameter default value and the target InliningThresholdMultiplier value tuned then respectively. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, eraman, hiraditya, haicheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64642 llvm-svn: 366348
* [ORC] Add deprecation warnings to ORCv1 layers and utilities.Lang Hames2019-07-174-27/+41
| | | | | | | | | | | | | | | | | Summary: ORCv1 is deprecated. The current aim is to remove it before the LLVM 10.0 release. This patch adds deprecation attributes to the ORCv1 layers and utilities to warn clients of the change. Reviewers: dblaikie, sgraenitz, AlexDenisov Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64609 llvm-svn: 366344
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