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| author | Craig Topper <craig.topper@intel.com> | 2019-07-18 06:18:06 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-07-18 06:18:06 +0000 |
| commit | 8da0402210232ba439493bf197865835fbf0600e (patch) | |
| tree | a331691d3a0b41944bc8ba73d339d9a8c7158415 /llvm/lib | |
| parent | 4f93b8b56f5982d19b8b55b8c575887c17e15588 (diff) | |
| download | bcm5719-llvm-8da0402210232ba439493bf197865835fbf0600e.tar.gz bcm5719-llvm-8da0402210232ba439493bf197865835fbf0600e.zip | |
[X86] Disable combineConcatVectors for vXi1 vectors.
I'm not convinced the code this calls is properly vetted for
vXi1 vectors. Experimental vector widening legalization testing
for D55251 is now hitting an assertion failure inside
EltsFromConsecutiveLoads. This is occurring from a v2i1 load
having a store size different than its VT size. Hopefully
this commit will keep such issues from happening.
llvm-svn: 366405
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 15d4bde0167..0b4bf687e6c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -43730,6 +43730,10 @@ static SDValue combineConcatVectors(SDNode *N, SelectionDAG &DAG, EVT SrcVT = N->getOperand(0).getValueType(); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + // Don't do anything for i1 vectors. + if (VT.getVectorElementType() == MVT::i1) + return SDValue(); + if (Subtarget.hasAVX() && TLI.isTypeLegal(VT) && TLI.isTypeLegal(SrcVT)) { SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end()); if (SDValue R = combineConcatVectorOps(SDLoc(N), VT.getSimpleVT(), Ops, DAG, |
