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* Fix typo.Richard Sandiford2013-12-241-1/+1
| | | | llvm-svn: 197986
* [SystemZ] Use interlocked-access 1 instructions for CodeGenRichard Sandiford2013-12-245-69/+118
| | | | | | | | | ...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. llvm-svn: 197985
* [SystemZ] Add MC support for interlocked-access 1 instructionsRichard Sandiford2013-12-245-3/+41
| | | | llvm-svn: 197984
* AVX-512: fixed some patterns for MVT::i1Elena Demikhovsky2013-12-243-19/+46
| | | | llvm-svn: 197981
* [AArch64]Add patterns to match normal shift nodes: shl, sra and srl.Hao Liu2013-12-241-0/+55
| | | | llvm-svn: 197969
* [AArch64 NEON] Fix a bug when lowering BUILD_VECTOR.Kevin Qin2013-12-241-1/+4
| | | | | | | | | DAG.getVectorShuffle() doesn't always return a vector_shuffle node. If mask is the exact sequence of it's operand(For example, operand_0 is v8i8, and the mask is 0, 1, 2, 3, 4, 5, 6, 7), it will directly return that operand. So a check is added here. llvm-svn: 197967
* [AArch64 NEON] Fix a pattern match failure with NEON_VDUP.Kevin Qin2013-12-242-6/+8
| | | | | | | | This failure caused by improper condition when lowering shuffle_vector to scalar_to_vector. After this patch NEON_VDUP with v1i64 will not be generated. llvm-svn: 197966
* [AArch64] Check fmul node single use in fused multiply patternsAna Pazos2013-12-242-10/+19
| | | | | | | | | | Check for single use of fmul node in fused multiply patterns to allow generation of fused multiply add/sub instructions. Otherwise fmul operation ends up being repeated more than once which does not help peformance on targets with only one MAC unit, as for example cortex-a53. llvm-svn: 197929
* [AArch64 NEON] Fixed fused multiply negate add/sub patternsAna Pazos2013-12-241-6/+6
| | | | | | | | | | | | | | | | | | The correct pattern matching should be: - fnmadd is (-Ra) + (-Rn)*Rm which should be matched as: fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra) and as (f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul FPR32:$Rn, FPR32:$Rm)))) - fnmsub is (-Ra) + Rn*Rm which should be matched as fma node:$Rn, node:$Rm, (fneg node:$Ra) and as (f32 (fsub (f32 (fmul FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)))) llvm-svn: 197928
* Debug info: Add enumerators to the __apple_names accelerator table.Adrian Prantl2013-12-231-0/+3
| | | | | | rdar://problem/11516681. llvm-svn: 197927
* Add support to indvars for optimizing sadd.with.overflow.Andrew Trick2013-12-232-4/+92
| | | | | | | | | | | | | | | | Split sadd.with.overflow into add + sadd.with.overflow to allow analysis and optimization. This should ideally be done after InstCombine, which can perform code motion (eventually indvars should run after all canonical instcombines). We want ISEL to recombine the add and the check, at least on x86. This is currently under an option for reducing live induction variables: -liv-reduce. The next step is reducing liveness of IVs that are live out of the overflow check paths. Once the related optimizations are fully developed, reviewed and tested, I do expect this to become default. llvm-svn: 197926
* Debug info: On ARM ensure that the data sections come before theAdrian Prantl2013-12-231-0/+13
| | | | | | | | | (optional) DWARF sections, so compiling with -g does not result in different code being generated. rdar://problem/15623193 llvm-svn: 197922
* ARM: bkpt has an implicit immediate constant 0Saleem Abdulrasool2013-12-232-0/+4
| | | | | | | | | The bkpt mnemonic has an implicit immediate constant of 0 unless otherwise specified. Add an instruction alias for the unvalued breakpoint mnemonic to treat it as a 0. This improves compatibility with GNU AS. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> llvm-svn: 197913
* Fix Scalarizer insertion point when replacing PHIs with insertelementsRichard Sandiford2013-12-231-1/+4
| | | | | | | | | | If the Scalarizer scalarized a vector PHI but could not scalarize all uses of it, it would insert a series of insertelements to reconstruct the vector PHI value from the scalar ones. The problem was that it would emit these insertelements immediately after the PHI, even if there were other PHIs after it. llvm-svn: 197909
* Fix Scalarizer handling of vector GEPs with multiple index operandsRichard Sandiford2013-12-231-11/+32
| | | | | | The old code only worked for one index operand. Also handle "inbounds". llvm-svn: 197908
* [asan] don't unpoison redzones on function exit in use-after-return mode.Kostya Serebryany2013-12-232-15/+57
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change the instrumented code before Ret instructions looked like: <Unpoison Frame Redzones> if (Frame != OriginalFrame) // I.e. Frame is fake <Poison Complete Frame> Now the instrumented code looks like: if (Frame != OriginalFrame) // I.e. Frame is fake <Poison Complete Frame> else <Unpoison Frame Redzones> Reviewers: eugenis Reviewed By: eugenis CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2458 llvm-svn: 197907
* [asan] produce fewer stores when poisoning stack shadowKostya Serebryany2013-12-231-20/+19
| | | | llvm-svn: 197904
* Use r2 when encoding tls on ppc32. Fixes PR18305.Roman Divacky2013-12-221-1/+2
| | | | llvm-svn: 197878
* Dwarf: Fix a copy-paste bug.Benjamin Kramer2013-12-221-1/+1
| | | | | | This tag isn't emitted by any compiler at the moment. PR18306. llvm-svn: 197877
* AVX512: SETCC returns i1 for AVX-512 and i8 for all othersElena Demikhovsky2013-12-222-2/+13
| | | | llvm-svn: 197876
* Add some comments.Roman Divacky2013-12-221-0/+2
| | | | llvm-svn: 197875
* TableGen: Generate valid identifiers for anonymous recordsAlp Toker2013-12-212-9/+11
| | | | | | | | | | Backends like OptParserEmitter assume that record names can be used as valid identifiers. The period '.' in generated anonymous names broke that assumption, causing a build-time error and in practice forcing all records to be named. llvm-svn: 197869
* Fix typo in assert message: s/load/storeMark Lacey2013-12-211-1/+1
| | | | llvm-svn: 197846
* BlockFrequencyInfo: Readded getEntryFreq.Yuchen Wu2013-12-201-0/+4
| | | | llvm-svn: 197839
* ARM AnalyzeBranch should ignore DEBUG_VALUES while analyzing terminators.Lang Hames2013-12-201-1/+1
| | | | | | Found by inspection by Julien Lerouge. Thanks Julian! llvm-svn: 197833
* clang-format a couple of mis-formatted functionsTimur Iskhodzhanov2013-12-201-14/+8
| | | | llvm-svn: 197831
* [COFF] Add support for the .secidx directiveTimur Iskhodzhanov2013-12-205-2/+44
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D2445 llvm-svn: 197826
* Implement initial-exec TLS for PPC32.Roman Divacky2013-12-205-13/+58
| | | | llvm-svn: 197824
* Support for microMIPS FPU instructions 1.Zoran Jovanovic2013-12-205-54/+269
| | | | llvm-svn: 197815
* Make this array const.Rafael Espindola2013-12-201-4/+4
| | | | llvm-svn: 197814
* [SystemZ] Optimize comparisons with truncated extended loadsRichard Sandiford2013-12-201-2/+24
| | | | | | | | | | | | If the extension of a loaded value is compared against zero and used in other arithmetic, InstCombine will change the comparison to use the unextended load. It's also possible that the comparison could be against the unextended load from the outset. In DAG form this becomes a truncation of an extending load. We want to strip the truncation if possible so that we can use load-and-test instructions. llvm-svn: 197804
* [SystemZ] Extend RISBG optimizationRichard Sandiford2013-12-201-3/+17
| | | | | | | | | | | | The handling of ANY_EXTEND and ZERO_EXTEND was too strict. In this context we can treat ZERO_EXTEND in much the same way as an AND and then also handle outermost ZERO_EXTENDs. I couldn't find a test that benefited from the ANY_EXTEND change, but it's more obvious to write it this way once SIGN_EXTEND and ZERO_EXTEND are handled differently. llvm-svn: 197802
* Add support for krait cpu in llvm::sys::getHostCPUName()Kai Nacke2013-12-201-0/+11
| | | | | | | Recently, support for krait cpu was added. This commit extends getHostCPUName() to return krait as cpu for the APQ8064 (a Krait 300). llvm-svn: 197792
* Transforms: Don't create bad weights when eliminating dead casesJustin Bogner2013-12-201-1/+1
| | | | | | | | | If we happen to eliminate every case in a switch that has branch weights, we currently try to create metadata for the one remaining branch, triggering an assert. Instead, we need to check that the metadata we're trying to create is sensible. llvm-svn: 197791
* ARM IAS: add support for the .pool directiveSaleem Abdulrasool2013-12-201-2/+2
| | | | | | | The .pool directive is an alias for the .ltorg directive used to create a literal pool. Simply treat .pool as if .ltorg was passed. llvm-svn: 197787
* R600: Allow ftruncTom Stellard2013-12-202-0/+5
| | | | | | | | | | | v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc v3: move ftrunc pattern next to TRUNC definition, it's available since R600 Patch By: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 197783
* Ranges in the .debug_range section need to have begin and end labels,Eric Christopher2013-12-201-13/+8
| | | | | | assert that this is so. llvm-svn: 197780
* Add support for a CU to output a set of ranges for the CU. This is usefulEric Christopher2013-12-202-20/+74
| | | | | | | | when you want to have the full list of addresses for a particular CU or when you have multiple modules linked together and can't depend upon the ordering of a single CU for begin/end ranges. llvm-svn: 197776
* When parsing data layout string looking for endianness, use the correct defaultDmitri Gribenko2013-12-201-1/+1
| | | | llvm-svn: 197771
* Correctly apply the default pointer sizeDmitri Gribenko2013-12-201-1/+1
| | | | llvm-svn: 197770
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-2010-135/+135
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* Fix documentation typosAlp Toker2013-12-201-1/+1
| | | | llvm-svn: 197757
* Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me withKevin Enderby2013-12-191-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this commit as the only one on the Blamelist so I quickly reverted this. However it was actually Nick's change who has since fixed that issue. Original commit message: Changed the X86 assembler for intel syntax to work with directional labels. The X86 assembler as a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following an Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197744
* Change getStringRepresentation to skip defaults.Rafael Espindola2013-12-191-17/+45
| | | | | | | | | | I have a pending change for clang to use getStringRepresentation to check that its DataLayout is in sync with llvm's. getStringRepresentation is not called from llvm itself, so far it is mostly a debugging aid, so the shorter strings are an independent improvement. llvm-svn: 197740
* Ensure deterministic when printing ARM assembler constant poolsDavid Peixotto2013-12-191-12/+24
| | | | | | | | | | | | | | | | We dump any non-empty assembler constant pools after a successful parse of an assembly file that uses the ldr pseudo opcode. These per-section constant pools should be output in a deterministic order to ensure that we always generate the same output when printing the output with an AsmStreamer. This patch changes the map data struture used to associate a section with its constant pool to a MapVector to ensure deterministic output. Because this map type does not support deletion, we now check that the constant pool is not empty before dumping its entries and clear the entries after emitting them with the streamer. llvm-svn: 197735
* Revert my change to the X86 assembler for intel syntax to work withKevin Enderby2013-12-191-34/+2
| | | | | | directional labels. Because it doesn't work for windows :) llvm-svn: 197731
* Changed the X86 assembler for intel syntax to work with directional labels.Kevin Enderby2013-12-191-2/+34
| | | | | | | | | | | | | | | | | | | | | | | The X86 assembler has a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following the Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197728
* Make sys::ThreadLocal<> zero-initialized on non-thread builds (PR18205)Hans Wennborg2013-12-192-2/+2
| | | | | | | | | | | | | According to the docs, ThreadLocal<>::get() should return NULL if no object has been set. This patch makes that the case also for non-thread builds and adds a very basic unit test to check it. (This was causing PR18205 because PrettyStackTraceHead didn't get zero- initialized and we'd crash trying to read past the end of that list. We didn't notice this so much on Linux since we'd crash after printing all the entries, but on Mac we print into a SmallString, and would crash before printing that.) llvm-svn: 197718
* Stay classy (and legal) LLVM. Remove links to 3rd party SMT solver whose ↵Kay Tiong Khoo2013-12-191-4/+2
| | | | | | links may not be permanent. llvm-svn: 197713
* [X86][fast-isel] Fix select lowering.Quentin Colombet2013-12-191-2/+7
| | | | | | | | | | The condition in selects is supposed to be i1. Make sure we are just reading the less significant bit of the 8 bits width value to match this constraint. <rdar://problem/15651765> llvm-svn: 197712
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