[X86][fast-isel] Fix select lowering.

The condition in selects is supposed to be i1.
Make sure we are just reading the less significant bit
of the 8 bits width value to match this constraint.

<rdar://problem/15651765>

llvm-svn: 197712

1 files changed, 7 insertions, 2 deletions

diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 972b82fa946..7be2a14a44f 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1508,8 +1508,13 @@ bool X86FastISel::X86SelectSelect(const Instruction *I) {
   unsigned Op2Reg = getRegForValue(I->getOperand(2));
   if (Op2Reg == 0) return false;
 
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
-    .addReg(Op0Reg).addReg(Op0Reg);
+  // Selects operate on i1, however, Op0Reg is 8 bits width and may contain
+  // garbage. Indeed, only the less significant bit is supposed to be accurate.
+  // If we read more than the lsb, we may see non-zero values whereas lsb
+  // is zero. Therefore, we have to truncate Op0Reg to i1 for the select.
+  // This is acheived by performing TEST against 1.
+  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
+    .addReg(Op0Reg).addImm(1);
   unsigned ResultReg = createResultReg(RC);
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
     .addReg(Op1Reg).addReg(Op2Reg);