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* [WebAssembly] Remove unused memory instructions and patternsThomas Lively2019-09-233-130/+0
| | | | | | | | | | | | | | | | Summary: Removes duplicated SIMD loads and store instructions and removes patterns involving GlobalAddresses that were not used in any tests. Reviewers: aheejin, sunfish Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67783 llvm-svn: 372648
* [X86] Use TargetConstant for condition code on X86ISD::SETCC/CMOV/BRCOND nodes.Craig Topper2019-09-234-141/+136
| | | | | | | | | | This removes the need for ConvertToTarget opcodes in the isel table. It's also consistent with the recent changes to use TargetConstant for intrinsic nodes that always take immediates. Differential Revision: https://reviews.llvm.org/D67902 llvm-svn: 372645
* [AMDGPU][MC] Corrected handling of relocatable expressionsDmitry Preobrazhensky2019-09-231-11/+20
| | | | | | | | | | See bug 43359: https://bugs.llvm.org//show_bug.cgi?id=43359 Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D67829 llvm-svn: 372622
* HexagonLoopIdiomRecognition - silence static analyzer dyn_cast<> null ↵Simon Pilgrim2019-09-231-3/+3
| | | | | | dereference warnings. NFCI. llvm-svn: 372619
* [Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVXKrzysztof Parzyszek2019-09-232-27/+26
| | | | llvm-svn: 372616
* [x86] fix assert with horizontal math + broadcast of vector (PR43402)Sanjay Patel2019-09-232-5/+6
| | | | | | https://bugs.llvm.org/show_bug.cgi?id=43402 llvm-svn: 372606
* Cosmetic; don't use the magic constant 35 when HASH is more readable. This ↵Mark Murray2019-09-232-16/+16
| | | | | | | | | | | | | | | | matches other MCK__<THING>_* usage better. Summary: No functional change. This fixes a magic constant in MCK__*_... macros only. Reviewers: ostannard Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67840 llvm-svn: 372599
* [Alignment][NFC] DataLayout migration to llvm::AlignGuillaume Chatelet2019-09-231-1/+1
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: jholewinski, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67914 llvm-svn: 372596
* [Alignment] Get DataLayout::StackAlignment as AlignGuillaume Chatelet2019-09-233-5/+8
| | | | | | | | | | | | | | | | | | | | Summary: Internally it is needed to know if StackAlignment is set but we can expose it as llvm::Align. This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67852 llvm-svn: 372585
* [ARM][MVE] Remove old tail predicatesSam Parker2019-09-232-9/+60
| | | | | | | | | | | Remove any predicate that we replace with a vctp intrinsic, and try to remove their operands too. Also look into the exit block to see if there's any duplicates of the predicates that we've replaced and clone the vctp to be used there instead. Differential Revision: https://reviews.llvm.org/D67709 llvm-svn: 372567
* [AArch64] support neon_sshl and neon_ushl in performIntrinsicCombine.Florian Hahn2019-09-231-0/+25
| | | | | | | | | | | | | | | | Try to generate ushll/sshll for aarch64_neon_ushl/aarch64_neon_sshl, if their first operand is extended and the second operand is a constant Also adds a few tests marked with FIXME, where we can further increase codegen. Reviewers: t.p.northover, samparker, dmgreen, anemet Reviewed By: anemet Differential Revision: https://reviews.llvm.org/D62308 llvm-svn: 372565
* [ARM][LowOverheadLoops] Use subs during revert.Sam Parker2019-09-231-16/+37
| | | | | | | | | | Check whether there are any uses or defs between the LoopDec and LoopEnd. If there's not, then we can use a subs to set the cpsr and skip generating a cmp. Differential Revision: https://reviews.llvm.org/D67801 llvm-svn: 372560
* [ARM][LowOverheadLoops] Use tBcc when revertingSam Parker2019-09-231-8/+11
| | | | | | | | | Check the branch target ranges and use a tBcc instead of t2Bcc when we can. Differential Revision: https://reviews.llvm.org/D67796 llvm-svn: 372557
* [MIPS GlobalISel] VarArg argument lowering, select G_VASTART and vacopyPetar Avramovic2019-09-235-6/+80
| | | | | | | | | | | | | | | | CC_Mips doesn't accept vararg functions for O32, so we have to explicitly use CC_Mips_FixedArg. For lowerCall we now properly figure out whether callee function is vararg or not, this has no effect for O32 since we always use CC_Mips_FixedArg. For lower formal arguments we need to copy arguments in register to stack and save pointer to start for argument list into MipsMachineFunction object so that G_VASTART could use it during instruction select. For vacopy we need to copy content from one vreg to another, load and store are used for that purpose. Differential Revision: https://reviews.llvm.org/D67756 llvm-svn: 372555
* [X86] Canonicalize all zeroes vector to RHS in X86DAGToDAGISel::tryVPTESTM.Craig Topper2019-09-231-3/+9
| | | | llvm-svn: 372544
* [X86] Remove SETEQ/SETNE canonicalization code from LowerIntVSETCC_AVX512 to ↵Craig Topper2019-09-232-9/+2
| | | | | | | | | | | | prevent an infinite loop. The attached test case would previous infinite loop after r365711. I'm going to move this to X86ISelDAGToDAG.cpp to get the setcc to match VPTEST in 32-bit mode in a follow up commit. llvm-svn: 372543
* Prefer AVX512 memcpy when applicableDavid Zarzycki2019-09-231-0/+5
| | | | | | | | | | | When AVX512 is available and the preferred vector width is 512-bits or more, we should prefer AVX512 for memcpy(). https://bugs.llvm.org/show_bug.cgi?id=43240 https://reviews.llvm.org/D67874 llvm-svn: 372540
* [X86] Convert to Constant arguments to MMX shift by i32 intrinsics to ↵Craig Topper2019-09-232-5/+8
| | | | | | | | | | | | | | TargetConstant during lowering. This allows us to use timm in the isel table which is more consistent with other intrinsics that take an immediate now. We can't declare the intrinsic as taking an ImmArg because we need to match non-constants to the shift by MMX register instruction which we do by mutating the intrinsic id during lowering. llvm-svn: 372537
* [X86] Remove stale FIXME.Craig Topper2019-09-231-1/+0
| | | | | | | This goes back to when MMX was migrated to intrinsic only. The hack referenced here has been gone for quite a while. llvm-svn: 372536
* [X86][SelectionDAGBuilder] Move the hack for handling MMX shift by i32 ↵Craig Topper2019-09-231-0/+52
| | | | | | | | | | | | | | | | | | | | | | intrinsics into the X86 backend. This intrinsics should be shift by immediate, but gcc allows any i32 scalar and clang needs to match that. So we try to detect the non-constant case and move the data from an integer register to an MMX register. Previously this was done by creating a v2i32 build_vector and bitcast in SelectionDAGBuilder. This had to be done early since v2i32 isn't a legal type. The bitcast+build_vector would be DAG combined to X86ISD::MMX_MOVW2D which isel will turn into a GPR->MMX MOVD. This commit just moves the whole thing to lowering and emits the X86ISD::MMX_MOVW2D directly to avoid the illegal type. The test changes just seem to be due to nodes being linearized in a different order. llvm-svn: 372535
* [X86] Require last argument to LWPINS/LWPVAL builtins to be an ICE. Add ↵Craig Topper2019-09-221-4/+4
| | | | | | | | ImmArg to the llvm intrinsics. Update the isel patterns to use timm instead of imm. llvm-svn: 372534
* [X86] X86DAGToDAGISel::matchBEXTRFromAndImm(): if can't use BEXTR, fallback ↵Roman Lebedev2019-09-221-12/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to BZHI is profitable (PR43381) Summary: PR43381 notes that while we are good at matching `(X >> C1) & C2` as BEXTR/BEXTRI, we only do that if we either have BEXTRI (TBM), or if BEXTR is marked as being fast (`-mattr=+fast-bextr`). In all other cases we don't match. But that is mainly only true for AMD CPU's. However, for all the CPU's for which we have sched models, the BZHI is always fast (or the sched models are all bad.) So if we decide that it's unprofitable to emit BEXTR/BEXTRI, we should consider falling-back to BZHI if it is available, and follow-up with the shift. While it's really tempting to do something because it's cool it is wise to first think whether it actually makes sense to do. We shouldn't just use BZHI because we can, but only it it is beneficial. In particular, it isn't really worth it if the input is a register, mask is small, or we can fold a load. But it is worth it if the mask does not fit into 32-bits. (careful, i don't know much about intel cpu's, my choice of `-mcpu` may be bad here) Thus we manage to fold a load: https://godbolt.org/z/Er0OQz Or if we'd end up using BZHI anyways because the mask is large: https://godbolt.org/z/dBJ_5h But this isn'r actually profitable in general case, e.g. here we'd increase microop count (the register renaming is free, mca does not model that there it seems) https://godbolt.org/z/k6wFoz Likewise, not worth it if we just get load folding: https://godbolt.org/z/1M1deG https://bugs.llvm.org/show_bug.cgi?id=43381 Reviewers: RKSimon, craig.topper, davezarzycki, spatel Reviewed By: craig.topper, davezarzycki Subscribers: andreadb, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67875 llvm-svn: 372532
* [AMDGPU] isSDNodeAlwaysUniform - silence static analyzer ↵Simon Pilgrim2019-09-221-3/+2
| | | | | | | | dyn_cast<LoadSDNode> null dereference warning. NFCI. The static analyzer is warning about a potential null dereference, but we should be able to use cast<LoadSDNode> directly and if not assert will fire for us. llvm-svn: 372528
* [X86] Fix some VCVTPS2PH isel patterns where 'i32' was used instead of 'timm'Craig Topper2019-09-222-14/+14
| | | | | | | This seems to have completed omitted any check for the opcode of the operand in the isel table. llvm-svn: 372526
* [X86][TableGen] Allow timm to appear in output patterns. Use it to remove ↵Craig Topper2019-09-223-119/+119
| | | | | | | | | | | | | | ConvertToTarget opcodes from the X86 isel table. We're now using a lot more TargetConstant nodes in SelectionDAG. But we were still telling isel to convert some of them to TargetConstants even though they already are. This is because isel emits a conversion anytime the output pattern has a an 'imm'. I guess for patterns in instructions we take the 'timm' from the 'set' pattern, but for Pat patterns with explcicit output we previously had to say 'imm' since 'timm' wasn't allowed in outputs. llvm-svn: 372525
* [X86] Update commutable EVEX vcmp patterns to use timm instead of imm.Craig Topper2019-09-221-6/+6
| | | | | | | We need to match TargetConstant, not Constant. This was broken in r372338, but we lacked test coverage. llvm-svn: 372523
* [Cost][X86] Add more missing vector truncation costsSimon Pilgrim2019-09-221-0/+6
| | | | | | The AVX512 cases still need some work to correct recognise the PMOV truncation cases. llvm-svn: 372514
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-09-221-1/+1
| | | | llvm-svn: 372508
* [AArch64] AArch64StackTagging - Silence static analyzer dyn_cast<> null ↵Simon Pilgrim2019-09-221-1/+1
| | | | | | | | dereference warning. NFCI. The static analyzer is warning about potential null dereferences, but we should be able to use cast<> directly and if not assert will fire for us. llvm-svn: 372507
* [NVPTX] NVPTXLowerAggrCopies - Silence static analyzer dyn_cast<StoreInst> ↵Simon Pilgrim2019-09-221-1/+1
| | | | | | null dereference warning. NFCI. llvm-svn: 372504
* [Lanai] LanaiAsmParser - Silence static analyzer dyn_cast null dereference ↵Simon Pilgrim2019-09-221-8/+9
| | | | | | | | warnings. NFCI. We were already doing this dyn_cast && isa<> && cast<> pattern for some add*Operands methods, just do this more consistently to stop clang static analyzer warning so much. llvm-svn: 372503
* AMDGPUPrintfRuntimeBinding - silence static analyzer null dereference ↵Simon Pilgrim2019-09-221-3/+2
| | | | | | warnings. NFCI. llvm-svn: 372501
* [MIPS] Don't dereference dyn_cast<> Constant results. NFCI.Simon Pilgrim2019-09-221-2/+2
| | | | | | The static analyzer is warning about potential null dereferences, but we should be able to use cast<> directly and if not assert will fire for us. llvm-svn: 372500
* [Hexagon] Don't dereference dyn_cast<ConstantFPSDNode> result. NFCI.Simon Pilgrim2019-09-221-1/+1
| | | | | | The static analyzer is warning about potential null dereference, but we should be able to use cast<ConstantFPSDNode> directly and if not assert will fire for us. llvm-svn: 372499
* [Cost][X86] Add v2i64 truncation costsSimon Pilgrim2019-09-221-0/+4
| | | | | | | | We are missing costs for a lot of truncation cases, I'm hoping to address all the 'zero cost' cases in trunc.ll I thought this was a vector widening side effect, but even before this we had some interesting LV decisions (notably over indvars) being made due to these zero costs. llvm-svn: 372498
* Move classes into anonymous namespaces. NFC.Benjamin Kramer2019-09-223-1/+5
| | | | llvm-svn: 372495
* [AArch64][GlobalISel] Implement selection for G_SHL of <2 x i64>Amara Emerson2019-09-211-1/+3
| | | | | | Simple continuation of existing selection support. llvm-svn: 372467
* [AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>Amara Emerson2019-09-211-1/+5
| | | | | | Just add an extra case to the existing selection logic. llvm-svn: 372466
* [AArch64][GlobalISel] Make <4 x s32> G_ASHR and G_LSHR legal.Amara Emerson2019-09-211-2/+6
| | | | llvm-svn: 372465
* [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCountJames Molloy2019-09-214-168/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommit: fix asan errors. The way MachinePipeliner uses these target hooks is stateful - we reduce trip count by one per call to reduceLoopCount. It's a little overfit for hardware loops, where we don't have to worry about stitching a loop induction variable across prologs and epilogs (the induction variable is implicit). This patch introduces a new API: /// Analyze loop L, which must be a single-basic-block loop, and if the /// conditions can be understood enough produce a PipelinerLoopInfo object. virtual std::unique_ptr<PipelinerLoopInfo> analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const; The return value is expected to be an implementation of the abstract class: /// Object returned by analyzeLoopForPipelining. Allows software pipelining /// implementations to query attributes of the loop being pipelined. class PipelinerLoopInfo { public: virtual ~PipelinerLoopInfo(); /// Return true if the given instruction should not be pipelined and should /// be ignored. An example could be a loop comparison, or induction variable /// update with no users being pipelined. virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0; /// Create a condition to determine if the trip count of the loop is greater /// than TC. /// /// If the trip count is statically known to be greater than TC, return /// true. If the trip count is statically known to be not greater than TC, /// return false. Otherwise return nullopt and fill out Cond with the test /// condition. virtual Optional<bool> createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &Cond) = 0; /// Modify the loop such that the trip count is /// OriginalTC + TripCountAdjust. virtual void adjustTripCount(int TripCountAdjust) = 0; /// Called when the loop's preheader has been modified to NewPreheader. virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0; /// Called when the loop is being removed. virtual void disposed() = 0; }; The Pipeliner (ModuloSchedule.cpp) can use this object to modify the loop while allowing the target to hold its own state across all calls. This API, in particular the disjunction of creating a trip count check condition and adjusting the loop, improves the code quality in ModuloSchedule.cpp. llvm-svn: 372463
* [X86] Use sse_load_f32/f64 and timm in patterns for memory form of ↵Craig Topper2019-09-211-4/+3
| | | | | | | | | | | | vgetmantss/sd. Previously we only matched scalar_to_vector and scalar load, but we should be able to narrow a vector load or match vzload. Also need to match TargetConstant instead of Constant. The register patterns were previously updated, but not the memory patterns. llvm-svn: 372458
* avr targetinfo: remove unneeded dep on MCNico Weber2019-09-211-2/+2
| | | | llvm-svn: 372451
* AMDGPU/GlobalISel: Allow selection of scalar min/maxMatt Arsenault2019-09-211-4/+4
| | | | | | | | | I believe all of the uniform/divergent pattern predicates are redundant and can be removed. The uniformity bit already influences the register class, and nothhing has broken when I've removed this and others. llvm-svn: 372450
* [SystemZ] Support z15 processor nameUlrich Weigand2019-09-205-36/+37
| | | | | | | | | | | The recently announced IBM z15 processor implements the architecture already supported as "arch13" in LLVM. This patch adds support for "z15" as an alternate architecture name for arch13. The patch also uses z15 in a number of places where we used arch13 as long as the official name was not yet announced. llvm-svn: 372435
* Fix missed case of switching getConstant to getTargetConstant. Try 2.Sterling Augustine2019-09-201-1/+1
| | | | | | | | | | | | | | Summary: This fixes a crasher introduced by r372338. Reviewers: echristo, arsenm Subscribers: wdng, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67850 llvm-svn: 372434
* [PPC] PPCLoopPreIncPrep - silence static analyzer null dereference warning.Simon Pilgrim2019-09-201-1/+1
| | | | llvm-svn: 372430
* Revert "[MachinePipeliner] Improve the TargetInstrInfo API ↵Mitch Phillips2019-09-204-170/+168
| | | | | | | | | | | analyzeLoop/reduceLoopCount" This commit broke the ASan buildbot. See comments in rL372376 for more information. This reverts commit 15e27b0b6d9d51362fad85dbe95ac5b3fadf0a06. llvm-svn: 372425
* [NFC][PowerPC] Refactor classifyGlobalReferenceJinsong Ji2019-09-205-28/+12
| | | | | | | | | | We always(and only) check the NLP flag after calling classifyGlobalReference to see whether it is accessed indirectly. Refactor to code to use isGVIndirectSym instead. llvm-svn: 372417
* [MTE] Handle MTE instructions in AArch64LoadStoreOptimizer.Evgeniy Stepanov2019-09-201-32/+98
| | | | | | | | | | | | | | Summary: Generate pre- and post-indexed forms of ST*G and STGP when possible. Reviewers: ostannard, vitalybuka Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67741 llvm-svn: 372412
* [SelectionDAG][Mips][Sparc] Don't allow SimplifyDemandedBits to constant ↵Craig Topper2019-09-201-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | fold TargetConstant nodes to a Constant. Summary: After the switch in SimplifyDemandedBits, it tries to create a constant when possible. If the original node is a TargetConstant the default in the switch will call computeKnownBits on the TargetConstant which will succeed. This results in the TargetConstant becoming a Constant. But TargetConstant exists to avoid being changed. I've fixed the two cases that relied on this in tree by explicitly making the nodes constant instead of target constant. The Sparc case is an old bug. The Mips case was recently introduced now that ImmArg on intrinsics gets turned into a TargetConstant when the SelectionDAG is created. I've removed the ImmArg since it lowers to generic code. Reviewers: arsenm, RKSimon, spatel Subscribers: jyknight, sdardis, wdng, arichardson, hiraditya, fedor.sergeev, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67802 llvm-svn: 372409
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