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* Fix assert.Eric Christopher2012-01-111-2/+2
| | | | llvm-svn: 147966
* Support segmented stacks on mac.Rafael Espindola2012-01-112-18/+68
| | | | | | | | This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support frames with static size Patch by Brian Anderson. llvm-svn: 147960
* Generate the segmented stack prologue for fastcc too.Rafael Espindola2012-01-111-1/+2
| | | | | | Patch by Brian Anderson. llvm-svn: 147958
* Revert r147945 which disabled an addressing mode transformation. I hadChandler Carruth2012-01-111-4/+0
| | | | | | | | | hoped this would revive one of the llvm-gcc selfhost build bots, but it didn't so it doesn't appear that my transform is the culprit. If anyone else is seeing failures, please let me know! llvm-svn: 147957
* Use unsigned comparison in segmented stack prologue.Rafael Espindola2012-01-111-1/+1
| | | | | | | | This is a comparison of two addresses, and GCC does the comparison unsigned. Patch by Brian Anderson. llvm-svn: 147954
* Explicitly set the scale to 1 on some segstack prologue instrs.Rafael Espindola2012-01-112-4/+4
| | | | | | Patch by Brian Anderson. llvm-svn: 147952
* Add XOP Intrinsics and testsJan Sjödin2012-01-111-73/+662
| | | | llvm-svn: 147949
* Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not ↵Nadav Rotem2012-01-111-4/+2
| | | | | | zero untouched elements. Use INSERT_VECTOR_ELT instead. llvm-svn: 147948
* Disable the transformation I added in r147936 to see if it fixes someChandler Carruth2012-01-111-0/+4
| | | | | | | | strange build bot failures that look like a miscompile into an infloop. I'll investigate this tomorrow, but I'd both like to know whether my patch is the culprit, and get the bots back to green. llvm-svn: 147945
* Hoist a really redundant code pattern into a helper function, and deleteChandler Carruth2012-01-111-80/+29
| | | | | | lots of lines of code. No functionality changed. llvm-svn: 147942
* Simplify the AND-rooted mask+shift checking code to match that of theChandler Carruth2012-01-111-8/+6
| | | | | | SRL-rooted code. llvm-svn: 147941
* Unify the interface of the three mask+shift transform helpers, andChandler Carruth2012-01-111-26/+34
| | | | | | | factor the differences that were hiding in one of them into its other caller, the SRL handling code. No change in behavior. llvm-svn: 147940
* Clarify and make explicit some of the requirements for transformingChandler Carruth2012-01-111-52/+64
| | | | | | | | | | mask+shift pairs at the beginning of the ISD::AND case block, and then hoist the final pattern into a helper function, simplifying and reflowing it appropriately. This should have no observable behavior change, but several simplifications fell out of this such as directly computing the new mask constant, etc. llvm-svn: 147939
* Fix undefined code and reenable test case.Jakob Stoklund Olesen2012-01-111-2/+2
| | | | | | | I don't think the compact encoding code is right, but at least is has defined behavior now. llvm-svn: 147938
* Hoist the logic to transform shift+mask combinations into sub-registerChandler Carruth2012-01-111-56/+68
| | | | | | | | extracts and scaled addressing modes into its own helper function. No functionality changed here, just hoisting and layout fixes falling out of that hoisting. llvm-svn: 147937
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-111-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
* Add big endian mips support. Based on a patch by Jack Carter.Rafael Espindola2012-01-113-16/+20
| | | | llvm-svn: 147924
* Add the skeleton of an asm parser for mips.Rafael Espindola2012-01-117-2/+114
| | | | llvm-svn: 147923
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-3/+4
| | | | | | | | Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 llvm-svn: 147922
* Fixed order of operands in comment to match code.Lang Hames2012-01-101-1/+1
| | | | llvm-svn: 147890
* Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.Joerg Sonnenberger2012-01-101-1/+1
| | | | | | | Add a test that checks the stack alignment of a simple function for Darwin, Linux and NetBSD for 32bit and 64bit mode. llvm-svn: 147888
* Consider unknown alignment caused by OptimizeThumb2Instructions().Jakob Stoklund Olesen2012-01-101-4/+25
| | | | | | | | | | | | | | | | | | | | This function runs after all constant islands have been placed, and may shrink some instructions to their 2-byte forms. This can actually cause some constant pool entries to move out of range because of growing alignment padding. Treat instructions that may be shrunk the same as inline asm - they erode the known alignment bits. Also reinstate an old assertion in verify(). It is correct now that basic block offsets include alignments. Add a single large test case that will hopefully exercise many parts of the constant island pass. <rdar://problem/10670199> llvm-svn: 147885
* Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a fewChad Rosier2012-01-101-2/+3
| | | | | | | failing test cases on our internal AVX nightly tester. rdar://10663637 llvm-svn: 147881
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-103-8/+8
| | | | | | rdar://10663487 llvm-svn: 147876
* Fix some leftover control reaches end of non-void function warnings.Benjamin Kramer2012-01-103-2/+4
| | | | llvm-svn: 147874
* Move default case for covered enum outside of switch.Richard Smith2012-01-101-1/+1
| | | | llvm-svn: 147870
* For i386, don't use the generic code.Bill Wendling2012-01-101-2/+3
| | | | | | | | | As the comment around 7746 says, it's better to use the x87 extended precision here than SSE. And the generic code doesn't know how to do that. It also regains the speed lost for the uint64_to_float.c testcase. <rdar://problem/10669858> llvm-svn: 147869
* Fix a -Wreturn-type warning in g++.Richard Smith2012-01-101-0/+1
| | | | llvm-svn: 147867
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-101-0/+1
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Add definition for intel asm variant.Devang Patel2012-01-101-1/+11
| | | | | | Right now, this just adds additional entries in match table. The parser does not use them yet. llvm-svn: 147859
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-1011-17/+0
| | | | llvm-svn: 147855
* Add definitions for AMD's bobcat (aka btver1)Benjamin Kramer2012-01-101-0/+5
| | | | llvm-svn: 147846
* Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. ↵Craig Topper2012-01-101-18/+20
| | | | | | There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside. llvm-svn: 147844
* Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is ↵Craig Topper2012-01-105-79/+77
| | | | | | the final piece to remove the AVX hack that disabled SSE. llvm-svn: 147843
* Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. ↵Craig Topper2012-01-102-31/+27
| | | | | | AVX is now an SSE level and no longer disables SSE checks. llvm-svn: 147842
* Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper2012-01-106-116/+89
| | | | | | predicates. Another commit will remove orAVX functions from X86SubTarget. llvm-svn: 147841
* Accurately model hardware alignment rounding.Jakob Stoklund Olesen2012-01-101-21/+56
| | | | | | | | | | | | | | | | | | | On Thumb, the displacement computation hardware uses the address of the current instruction rouned down to a multiple of 4. Include this rounding in the UserOffset we compute for each instruction. When inline asm is present, the instruction alignment may not be known. Constrain the maximum displacement instead in that case. This makes it possible for CreateNewWater() and OffsetIsInRange() to agree about the valid displacements. When they disagree, infinite looping happens. As always, test cases for this stuff are insane. <rdar://problem/10660175> llvm-svn: 147825
* Remove the logging streamer.Rafael Espindola2012-01-101-3/+0
| | | | llvm-svn: 147820
* Catch runaway ARMConstantIslandPass even in -Asserts builds.Jakob Stoklund Olesen2012-01-091-2/+2
| | | | | | | | | The pass is prone to looping, and it is better to crash than loop forever, even in a -Asserts build. <rdar://problem/10660175> llvm-svn: 147806
* Fix asm string wrt variants.Devang Patel2012-01-092-7/+7
| | | | llvm-svn: 147805
* Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel2012-01-091-2/+4
| | | | | | | AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
* Don't rely on the fact that shift values are never very large, and thusChandler Carruth2012-01-091-1/+1
| | | | | | | | | | | | this substraction will result in small negative numbers at worst which become very large positive numbers on assignment and are thus caught by the <=4 check on the next line. The >0 check clearly intended to catch these as negative numbers. Spotted by inspection, and impossible to trigger given the shift widths that can be used. llvm-svn: 147773
* Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. ↵Craig Topper2012-01-093-32/+22
| | | | | | Predicate functions have been altered to maintain previous names and behavior. llvm-svn: 147770
* Add HasAVX predicate to some of the AVX patterns.Craig Topper2012-01-091-0/+17
| | | | llvm-svn: 147769
* Reorder a bunch of patterns to put the AVX version first thus giving it ↵Craig Topper2012-01-091-405/+407
| | | | | | priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget. llvm-svn: 147768
* Clean up patterns for MOVNT*. Not sure why there were floating point types ↵Craig Topper2012-01-091-17/+3
| | | | | | on MOVNTPS and MOVNTDQ. And v4i64 was completely missing. llvm-svn: 147767
* Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no ↵Craig Topper2012-01-091-2/+2
| | | | | | AVX equivalent so we should use the SSE version. llvm-svn: 147766
* Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical ↵Craig Topper2012-01-091-47/+63
| | | | | | operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues. llvm-svn: 147765
* Change some places that were checking for AVX OR SSE1/2 to use ↵Craig Topper2012-01-092-6/+6
| | | | | | hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h llvm-svn: 147764
* Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper2012-01-094-28/+52
| | | | | | instructions that were added along with SSE instructions to check for AVX in addition to SSE level. llvm-svn: 147762
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