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* [fast-isel] Add support for returning non-legal types with no sign- or zero-Chad Rosier2012-02-171-6/+6
| | | | | | entend flag. llvm-svn: 150774
* Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ↵Lang Hames2012-02-171-1/+0
| | | | | | bail on reserved registers. This *should* be safe as of r150786. llvm-svn: 150769
* Remove comment.Akira Hatanaka2012-02-161-2/+0
| | | | llvm-svn: 150739
* Remove unnecessary assignment to temporary, ResultReg.Chad Rosier2012-02-161-13/+8
| | | | llvm-svn: 150737
* Remove the YMM_HI_6_15 hack.Jakob Stoklund Olesen2012-02-161-7/+0
| | | | | | | | | Call clobbers are now represented with register mask operands. The regmask can easily represent the fact that xmm6 is call-preserved while ymm6 isn't. This is automatically computed by TableGen from the CalleeSavedRegs containing xmm6. llvm-svn: 150709
* Use the same CALL instructions for Windows as for everything else.Jakob Stoklund Olesen2012-02-169-87/+32
| | | | | | | The different calling conventions and call-preserved registers are represented with regmask operands that are added dynamically. llvm-svn: 150708
* Remove trailing whitespace. Add newline.Akira Hatanaka2012-02-161-2/+2
| | | | llvm-svn: 150706
* Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames2012-02-161-0/+1
| | | | llvm-svn: 150655
* FPSCR shouldn't be reserved.Lang Hames2012-02-161-1/+0
| | | | llvm-svn: 150654
* Enable register mask operands for x86 calls.Jakob Stoklund Olesen2012-02-163-40/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call instructions no longer have a list of 43 call-clobbered registers. Instead, they get a single register mask operand with a bit vector of call-preserved registers. This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call instruction, and it speeds up building call instructions because those 43 imp-def operands no longer need to be added to use-def lists. (And removed and shifted and re-added for every explicit call operand). Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and BranchFolding are significantly faster because they can deal with call clobbers in bulk. Overall, clang -O2 is between 0% and 8% faster, uniformly distributed depending on call density in the compiled code. Debug builds using clang -O0 are 0% - 3% faster. I have verified that this patch doesn't change the assembly generated for the LLVM nightly test suite when building with -disable-copyprop and -disable-branch-fold. Branch folding behaves slightly differently in a few cases because call instructions have different hash values now. Copy propagation flushes its data structures when it crosses a register mask operand. This causes it to leave a few dead copies behind, on the order of 20 instruction across the entire nightly test suite, including SPEC. Fixing this properly would require the pass to use different data structures. llvm-svn: 150638
* Optimize redundant sign extends and negation of predicates.Sirish Pande2012-02-1515-209/+1037
| | | | llvm-svn: 150606
* Revert "Replacing HexagonOptimizeSZExtends with HexagonPeephole."Eric Christopher2012-02-152-292/+129
| | | | | | This reverts commit 1656806a944bbd23e98c6e578810fe02495ab741. llvm-svn: 150605
* Revert "Optimize redundant sign extends and negation of predicates"Eric Christopher2012-02-1513-745/+80
| | | | | | | | as it's breaking the build. This reverts commit 11241abca5e2a313412fed594bb9d9fa2a2057fb. llvm-svn: 150604
* Replacing HexagonOptimizeSZExtends with HexagonPeephole.Sirish Pande2012-02-152-129/+292
| | | | llvm-svn: 150603
* Optimize redundant sign extends and negation of predicatesSirish Pande2012-02-1513-80/+745
| | | | llvm-svn: 150601
* Add braces to if clause to make symmetric with associate else clause.Chad Rosier2012-02-151-18/+19
| | | | llvm-svn: 150591
* Strip the pointer casts from the constants here.Bill Wendling2012-02-151-1/+1
| | | | | | | | | The c'tor list is stored as a list of 'void ()*'s, so all of the functions are bitcast to that. However, the dyn_cast doesn't automagically look through bitcasts. Do that for it. <rdar://problem/10813350> llvm-svn: 150572
* Added TargetPassConfig::disablePass/substitutePass as a general mechanism to ↵Andrew Trick2012-02-151-4/+4
| | | | | | override specific passes. llvm-svn: 150562
* Use a temporary variable, rather then a series of redundant calls.Chad Rosier2012-02-151-4/+5
| | | | llvm-svn: 150538
* Stop custom lowering forr x86 DEC64m from happening if the load in the ↵Pete Cooper2012-02-151-0/+1
| | | | | | lowered sequence has more than 1 user llvm-svn: 150537
* Use a temporary variable, rather then a series of redundant calls.Chad Rosier2012-02-151-4/+5
| | | | llvm-svn: 150536
* Remove unnecessary assignment to temporary, ResultReg.Chad Rosier2012-02-141-8/+4
| | | | llvm-svn: 150520
* Move old movl vector_shuffle patterns. Not needed anymore since ↵Craig Topper2012-02-142-63/+7
| | | | | | vector_shuffles shouldn't reach isel. llvm-svn: 150462
* Third time's the charm...?Lang Hames2012-02-141-2/+2
| | | | llvm-svn: 150447
* Unswap swap operands, partially reducing confusion.Lang Hames2012-02-141-2/+2
| | | | llvm-svn: 150444
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-4/+9
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* Make operands for VSWP read-modify-write.Lang Hames2012-02-131-4/+6
| | | | llvm-svn: 150433
* Still more vector_shuffle pattern removal.Craig Topper2012-02-132-39/+9
| | | | llvm-svn: 150365
* Fix various issues (or do cleanups) found by enabling certain MSVC warnings.Ahmed Charles2012-02-131-1/+4
| | | | | | | | | - Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default. - Remove misplaced llvm_unreachable. - Add static to a declaration of a function on MSVC x86 only. - Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable. llvm-svn: 150364
* Remove more vector_shuffle patterns for unpack. These should be target ↵Craig Topper2012-02-131-108/+40
| | | | | | specific nodes when they get to isel. llvm-svn: 150363
* Recommit r150328. Previous test failures should be fixed by r150360.Craig Topper2012-02-132-124/+37
| | | | llvm-svn: 150362
* Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only ↵Craig Topper2012-02-131-1/+4
| | | | | | have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel. llvm-svn: 150360
* Revert r150328, "Remove more vector_shuffle patterns."NAKAMURA Takumi2012-02-132-11/+98
| | | | | | It caused 3 failures on pre-penryn and non-x86(generic) hosts. llvm-svn: 150357
* Fixed bug when custom lowering DEC64m on x86.Pete Cooper2012-02-131-0/+1
| | | | | | | | | If the DEC node had more than one user, it was doing this lowering but leaving the original DEC node around and so decrementing twice. Fixes PR11964. llvm-svn: 150356
* Remove more vector_shuffle patterns.Craig Topper2012-02-122-98/+11
| | | | llvm-svn: 150328
* Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI callsNick Lewycky2012-02-121-1/+5
| | | | | | to TargetLibraryInfo and use one of them in GlobalOpt. llvm-svn: 150323
* Remove more vector_shuffle patterns.Craig Topper2012-02-122-78/+4
| | | | llvm-svn: 150321
* Remove more vector_shuffle patterns.Craig Topper2012-02-111-46/+4
| | | | llvm-svn: 150314
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-116-3/+80
| | | | | | Patch by Kai Nacke! llvm-svn: 150307
* Don't mix declarations and code.Benjamin Kramer2012-02-112-8/+6
| | | | llvm-svn: 150305
* Make the EDis tables const.Benjamin Kramer2012-02-115-8/+8
| | | | llvm-svn: 150304
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-115-15/+37
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. llvm-svn: 150303
* Remove some patterns for matching vector_shuffle instructions since ↵Craig Topper2012-02-112-78/+16
| | | | | | vector_shuffles should be custom lowered before isel. llvm-svn: 150299
* Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle ↵Craig Topper2012-02-111-36/+23
| | | | | | mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel. llvm-svn: 150296
* Revert r150222, as the clang driver now handles this properly.Jim Grosbach2012-02-101-11/+3
| | | | | | | Now that the clang driver passes the CPU and feature information to the backend when processing assembly files (150273), this isn't necessary. llvm-svn: 150274
* Make valgrind happy.Jason W Kim2012-02-101-2/+2
| | | | llvm-svn: 150251
* unnecessary includeAndrew Trick2012-02-101-1/+0
| | | | llvm-svn: 150228
* PTX no longer needs to provide its own backend.Andrew Trick2012-02-102-255/+21
| | | | llvm-svn: 150227
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-103-8/+3
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach2012-02-101-3/+11
| | | | | | rdar://10838899 llvm-svn: 150222
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