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* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0721-63/+75
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-074-27/+30
| | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
* R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2013-06-072-64/+66
| | | | | | | This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
* R600: Remove unnecessary includeTom Stellard2013-06-073-2/+4
| | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183558
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-071-38/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. llvm-svn: 183551
* R600: Don't compare iterators of different maps.Benjamin Kramer2013-06-071-1/+1
| | | | | | Found be libstdc's debug mode. llvm-svn: 183549
* Vincent says the element is at most once in the vector, so we don't need a ↵Benjamin Kramer2013-06-071-3/+7
| | | | | | full std::remove. llvm-svn: 183541
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-1/+1
| | | | | | I am able to compile/assemble/link/run /bin/echo from FreeBSD. llvm-svn: 183537
* R600: Fix a potential iterator invalidation issue.Benjamin Kramer2013-06-071-5/+3
| | | | | | As a bonus this reduces the loop from O(n^2) to O(n). llvm-svn: 183532
* R600: Remove an extra break in R600OptimizeVectorRegisters.cppVincent Lejeune2013-06-071-3/+1
| | | | llvm-svn: 183528
* Fold variable that's only used in assert into the assert.Benjamin Kramer2013-06-071-2/+1
| | | | | | Avoids unused variable warnings in Release builds. llvm-svn: 183512
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-077-20/+27
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183494
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0711-40/+67
| | | | | | the internals of TargetMachine could change. llvm-svn: 183493
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-073-6/+5
| | | | | | the internals of TargetMachine could change. llvm-svn: 183492
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-10/+6
| | | | | | the internals of TargetMachine could change. llvm-svn: 183491
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-079-19/+25
| | | | | | the internals of TargetMachine could change. llvm-svn: 183490
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0715-42/+48
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-076-28/+22
| | | | | | These objects are internal to the TargetMachine object and may change. llvm-svn: 183485
* ARM sched model: Use the right resources for DIVArnold Schwaighofer2013-06-071-1/+1
| | | | llvm-svn: 183477
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-071-0/+16
| | | | | | Reapply 183271. llvm-svn: 183472
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-071-0/+364
| | | | | | | | Reapply 183270 again (because three is a magic number). This should now no longer seg fault after r183459. llvm-svn: 183464
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-073-17/+19
| | | | llvm-svn: 183463
* R600: Rewrite an awkward loop in R600MachineSchedulerVincent Lejeune2013-06-061-7/+15
| | | | llvm-svn: 183458
* Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"Arnold Schwaighofer2013-06-061-364/+0
| | | | | | Breaks linux build bots (I thought the problem was something else). llvm-svn: 183447
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+364
| | | | | | Reapply 183270. llvm-svn: 183445
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-063-0/+125
| | | | | | Reapply 183269. llvm-svn: 183441
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+209
| | | | | | Reapply 183268. llvm-svn: 183438
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-061-0/+155
| | | | | | Reapply 183267. llvm-svn: 183436
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-061-4/+45
| | | | | | | | Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-061-18/+21
| | | | | | Reapply 183265. llvm-svn: 183432
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-061-11/+15
| | | | | | Reapply 183264. llvm-svn: 183430
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-061-27/+35
| | | | | | Reapply 183263. llvm-svn: 183428
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-061-3/+6
| | | | | | Reapply 183262. llvm-svn: 183427
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-061-2/+4
| | | | | | Reapply 183261. llvm-svn: 183425
* ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer2013-06-061-46/+61
| | | | | | Reapply of 183260. llvm-svn: 183423
* ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer2013-06-061-52/+86
| | | | | | Reapply of 183259. llvm-svn: 183421
* R600: Remove leftover code in R600MachineScheduler.cppVincent Lejeune2013-06-061-16/+0
| | | | | | Spotted by Benjamin Kramer. llvm-svn: 183413
* Cast to the correct type. Pointer, not reference.Bill Wendling2013-06-061-1/+1
| | | | llvm-svn: 183385
* R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized]NAKAMURA Takumi2013-06-061-1/+1
| | | | | FIXME: Is it false alarm? llvm-svn: 183371
* R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable]NAKAMURA Takumi2013-06-061-0/+1
| | | | llvm-svn: 183370
* Trailing linefeed.NAKAMURA Takumi2013-06-061-1/+0
| | | | llvm-svn: 183369
* Cast to the proper type.Bill Wendling2013-06-061-1/+1
| | | | llvm-svn: 183365
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-0612-39/+39
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* R600: Replace predicate loop with predicate functionTom Stellard2013-06-051-11/+13
| | | | llvm-svn: 183351
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-054-0/+370
| | | | | | | Previously commited @183279 but tests were failing, reverted @183286 It was broken because @183336 was missing, now it's there. llvm-svn: 183343
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-052-1/+32
| | | | | | It allows regalloc pass to remove them by trivially assigning associated reg llvm-svn: 183336
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+4
| | | | llvm-svn: 183334
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-052-1/+5
| | | | | | | | | | | | Add earlyclobber constaints to prevent input register being allocated as the output register because, according to Intel spec [1], "If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault." --- [1] http://software.intel.com/sites/default/files/319433-014.pdf llvm-svn: 183327
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-051-37/+49
| | | | | | Reapply of 183258. llvm-svn: 183321
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-054-7/+89
| | | | | | | | Add some generic SchedWrites and assign resources for Swift and Cortex A9. Reapply of r183257. (Removed empty InstRW for division on swift) llvm-svn: 183319
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