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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-06 18:06:30 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-06 18:06:30 +0000 |
| commit | 577279778e05f1ddd7344681bde913d70000ae62 (patch) | |
| tree | d41a977b06a328ec2f41f973069ecfab006c0e46 /llvm/lib/Target | |
| parent | 8f58b730ab42639a337df2e1d0297b13e81b9e53 (diff) | |
| download | bcm5719-llvm-577279778e05f1ddd7344681bde913d70000ae62.tar.gz bcm5719-llvm-577279778e05f1ddd7344681bde913d70000ae62.zip | |
ARM sched model: Add preload thumb2 instructions
Reapply 183262.
llvm-svn: 183427
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 94e3fb18e81..d9615e0acb5 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -1539,7 +1539,8 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, "\t$addr", - [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> { + [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>, + Sched<[WritePreLd]> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; let Inst{22} = 0; @@ -1556,7 +1557,8 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc, "\t$addr", - [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> { + [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>, + Sched<[WritePreLd]> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; let Inst{23} = 0; // U = 0 @@ -1573,7 +1575,8 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, "\t$addr", - [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> { + [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>, + Sched<[WritePreLd]> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; let Inst{23} = 0; // add = TRUE for T1 |
