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* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-051-0/+2
| | | | | | | | An instruction with less than 3 inputs is trivially a fast immediate shift. Reapply of 183256, should not have caused the tablegen segfault on linux either. llvm-svn: 183314
* This is a simple patch that changes RRX and RRXS to accept all registers as ↵Mihai Popa2013-06-051-1/+1
| | | | | | | | operands. According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. llvm-svn: 183307
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-053-4/+40
| | | | | Reviewed-by: vljn at ovi.com llvm-svn: 183294
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-054-370/+0
| | | | | | This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing. llvm-svn: 183286
* Handle relocations that don't point to symbols.Rafael Espindola2013-06-052-11/+10
| | | | | | | | In ELF (as in MachO), not all relocations point to symbols. Represent this properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj ELF's dumper to handle relocatios without symbols. llvm-svn: 183284
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-044-0/+370
| | | | llvm-svn: 183279
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-045-47/+186
| | | | llvm-svn: 183278
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-041-1/+2
| | | | llvm-svn: 183275
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-048-1277/+207
| | | | llvm-svn: 183273
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-041-0/+16
| | | | llvm-svn: 183271
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+364
| | | | llvm-svn: 183270
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-041-0/+120
| | | | llvm-svn: 183269
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+209
| | | | llvm-svn: 183268
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-041-0/+155
| | | | llvm-svn: 183267
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-041-4/+45
| | | | | | Add more InstRW mappings. llvm-svn: 183266
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-041-18/+21
| | | | llvm-svn: 183265
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-041-11/+15
| | | | llvm-svn: 183264
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-041-27/+35
| | | | llvm-svn: 183263
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-041-3/+6
| | | | llvm-svn: 183262
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-041-2/+4
| | | | llvm-svn: 183261
* ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer2013-06-041-46/+61
| | | | llvm-svn: 183260
* ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer2013-06-041-52/+86
| | | | llvm-svn: 183259
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-041-37/+49
| | | | llvm-svn: 183258
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-044-7/+89
| | | | | | Add some generic SchedWrites and assign resources for Swift and Cortex A9. llvm-svn: 183257
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-041-0/+2
| | | | | | An instruction with less than 3 inputs is trivially a fast immediate shift. llvm-svn: 183256
* Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju2013-06-0419-154/+157
| | | | llvm-svn: 183243
* ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer2013-06-041-0/+1
| | | | | | | | | | The ARM backend did not expect LDRBi12 to hold a constant pool operand. Allow for LLVM to deal with the instruction similar to how it deals with LDRi12. This fixes PR16215. llvm-svn: 183238
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-042-20/+126
| | | | llvm-svn: 183229
* Test commit for user vmedic, to verify commit access. One line of comment is ↵Vladimir Medic2013-06-041-1/+1
| | | | | | added to MipsAsmParser.cpp. llvm-svn: 183215
* Silencing an MSVC warning about mixing bool and unsigned int.Aaron Ballman2013-06-041-1/+1
| | | | llvm-svn: 183176
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-033-15/+88
| | | | llvm-svn: 183138
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-033-9/+39
| | | | llvm-svn: 183137
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-032-0/+19
| | | | llvm-svn: 183136
* R600/SI: Adjust some instructions' out register class after ISelTom Stellard2013-06-032-0/+52
| | | | | | | This is necessary to avoid generating VGPR to SGPR copies in some cases. llvm-svn: 183135
* R600/SI: Handle REG_SEQUENCE in fitsRegClass()Tom Stellard2013-06-031-3/+13
| | | | llvm-svn: 183134
* R600/SI: Handle nodes with glue results correctly ↵Tom Stellard2013-06-031-0/+16
| | | | | | SITargetLowering::foldOperands() llvm-svn: 183133
* R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()Tom Stellard2013-06-031-5/+33
| | | | | | | | | | The CopyToReg nodes will sometimes try to copy a value from a VGPR to an SGPR. This kind of copy is not possible, so we need to detect VGPR->SGPR copies and do something else. The current strategy is to replace these copies with VGPR->VGPR copies and hope that all the users of CopyToReg can accept VGPRs as arguments. llvm-svn: 183132
* R600/SI: Add support for global loadsTom Stellard2013-06-033-4/+39
| | | | llvm-svn: 183131
* R600/SI: Rework MUBUF store instructionsTom Stellard2013-06-035-42/+71
| | | | | | | The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. llvm-svn: 183130
* R600: 3 op instructions have no write bit but the result are store in PVVincent Lejeune2013-06-031-3/+1
| | | | llvm-svn: 183111
* R600: CALL_FS consumes a stack size entryVincent Lejeune2013-06-031-0/+1
| | | | llvm-svn: 183108
* R600: use capital letter for PV channelVincent Lejeune2013-06-031-4/+4
| | | | llvm-svn: 183107
* R600: Constraints input regs of interp_xy,_zwVincent Lejeune2013-06-032-11/+15
| | | | llvm-svn: 183106
* X86: sub_xmm registers are 128 bits wide.Ahmed Bougacha2013-06-031-1/+1
| | | | llvm-svn: 183103
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-034-0/+37
| | | | llvm-svn: 183094
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-032-0/+8
| | | | | | using two instructions (sethi and store). llvm-svn: 183090
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-021-22/+177
| | | | llvm-svn: 183088
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-021-1/+1
| | | | llvm-svn: 183083
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ↵Venkatraman Govindaraju2013-06-011-0/+6
| | | | | | as non-leaf functions. llvm-svn: 183079
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-014-155/+54
| | | | | | Very sorry, it was committed from the wrong branch by mistake. llvm-svn: 183070
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