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* Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add ↵Johnny Chen2011-03-282-5/+18
| | | | | | | | some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417
* ptx: clean up branch code a bitChe-Liang Chiou2011-03-283-16/+17
| | | | llvm-svn: 128405
* Make helper static.Benjamin Kramer2011-03-261-2/+2
| | | | llvm-svn: 128338
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-262-10/+39
| | | | llvm-svn: 128322
* Fix the bfi handling for or (and a mask) (and b mask). We need the twoEric Christopher2011-03-261-9/+10
| | | | | | | | | | | | | | masks to match inversely for the code as is to work. For the example given we actually want: bfi r0, r2, #1, #1 not #0, however, given the way the pattern is written it's not possible at the moment. Fixes rdar://9177502 llvm-svn: 128320
* Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode ↵Johnny Chen2011-03-251-6/+6
| | | | | | | | | | GPRRegClassID. Also add some test cases. rdar://problem/9189829 llvm-svn: 128304
* DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to ↵Johnny Chen2011-03-251-2/+3
| | | | | | | | RegClass. Add two test cases. rdar://problem/9182892 llvm-svn: 128299
* Modify DisassembleThumb2LdStEx() to be more robust/correct in light of ↵Johnny Chen2011-03-251-6/+6
| | | | | | | | recent change to t2LDREX/t2STREX instructions. Add two test cases. llvm-svn: 128293
* Add a note.Benjamin Kramer2011-03-251-0/+19
| | | | llvm-svn: 128286
* Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. ↵Johnny Chen2011-03-251-0/+5
| | | | | | | | Modify the disassembler to handle that. rdar://problem/9184053 llvm-svn: 128285
* Also need to handle invalid imod values for CPS2p.Johnny Chen2011-03-251-4/+11
| | | | | | rdar://problem/9186136 llvm-svn: 128283
* Ignore special ARM allocation hints for unexpected register classes.Jakob Stoklund Olesen2011-03-251-0/+4
| | | | | | | | | Add an assertion to linear scan to prevent it from allocating registers outside the register class. <rdar://problem/9183021> llvm-svn: 128254
* Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the ↵Johnny Chen2011-03-251-9/+9
| | | | | | | | register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. llvm-svn: 128252
* Suppress an unused variable warning in -asserts buildsMatt Beaumont-Gay2011-03-241-0/+1
| | | | llvm-svn: 128244
* Handle the added VBICiv*i* NEON instructions, too.Johnny Chen2011-03-241-2/+7
| | | | llvm-svn: 128243
* Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!Johnny Chen2011-03-241-3/+1
| | | | llvm-svn: 128241
* T2 Load/Store Multiple:Johnny Chen2011-03-241-1/+1
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240
* Plug a leak in the arm disassembler and put the tests back.Benjamin Kramer2011-03-241-3/+2
| | | | llvm-svn: 128238
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-246-60/+104
| | | | llvm-svn: 128236
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-1/+1
| | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
* Clean up assembly statement separator support.Jim Grosbach2011-03-241-3/+4
| | | | | | | | The MC asm lexer wasn't honoring a non-default (anything but ';') statement separator. Fix that, and generalize a bit to support multi-character statement separators. llvm-svn: 128227
* The r118201 added support for VORR (immediate). Update ↵Johnny Chen2011-03-241-0/+16
| | | | | | | | ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. llvm-svn: 128226
* Add comments to the handling of opcode CPS3p to reject invalid instruction ↵Johnny Chen2011-03-241-0/+2
| | | | | | | | encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. llvm-svn: 128220
* Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.NAKAMURA Takumi2011-03-243-62/+106
| | | | | FIXME: Some cleanups would be needed. llvm-svn: 128206
* Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntryEvan Cheng2011-03-241-5/+12
| | | | | | | | | | | | entries being compared may not be ARMConstantPoolValue. Without checking whether they are ARMConstantPoolValue first, and if the stars and moons are aligned properly, the equality test may return true (when the first few words of two Constants' values happen to be identical) and very bad things can happen. rdar://9125354 llvm-svn: 128203
* CPS3p: Let's reject impossible imod values by returning false from the ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | DisassembleMiscFrm() function. Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing) Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- Before: cpsUnknown imod operand UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123! After: /Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding 0x93 0x1c 0x2 0xf1 ^ llvm-svn: 128192
* Load/Store Multiple:Johnny Chen2011-03-241-4/+4
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. llvm-svn: 128191
* STRT and STRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-241-2/+2
| | | | | | | | refactorings (r119821). We now tag them as IndexModePost. llvm-svn: 128189
* The r128103 fix to cope with the removal of addressing modes from the MC ↵Johnny Chen2011-03-241-2/+7
| | | | | | | | | | instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186
* Enable GlobalMerge on darwin.Devang Patel2011-03-231-6/+0
| | | | llvm-svn: 128183
* Revert r128175.Andrew Trick2011-03-231-73/+4
| | | | | | I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix. llvm-svn: 128181
* Cmp peephole optimization isn't always safe for signed arithmetics.Evan Cheng2011-03-231-3/+43
| | | | | | | | | | | | | | | | | | | | | int tries = INT_MAX; while (tries > 0) { tries--; } The check should be: subs r4, #1 cmp r4, #0 bgt LBB0_1 The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop canonicalization apparently does in this case). cmp #0 would have cleared it while not changing the N and Z bits. Since BGT is dependent on the V bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0. rdar://9172742 llvm-svn: 128179
* Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.Andrew Trick2011-03-231-4/+73
| | | | | | (target-specific branchless method for double-width relational comparisons on x86) llvm-svn: 128175
* The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.Owen Anderson2011-03-231-1/+1
| | | | | | This fixes 464.h264ref with the integrated assembler. llvm-svn: 128172
* PTX: Improve support for 64-bit addressingJustin Holewinski2011-03-233-21/+72
| | | | | | | | | - Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses - Add comparison selection for i64 - Add zext selection for i32 -> i64 - Add shl/shr/sha support for i64 llvm-svn: 128153
* For ARM Disassembler, start a newline to dump the opcode and friends for an ↵Johnny Chen2011-03-221-1/+1
| | | | | | | | instruction. Change inspired by llvm-bug 9530 submitted by Jyun-Yan You. llvm-svn: 128122
* LDRT and LDRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-221-2/+2
| | | | | | | | | | refactorings (r119821). We now tag them as IndexModePost. This fixed http://llvm.org/bugs/show_bug.cgi?id=9530. llvm-svn: 128113
* A bit more analysis of a memset-related README entry.Eli Friedman2011-03-221-4/+5
| | | | llvm-svn: 128107
* A8.6.399 VSTM:Johnny Chen2011-03-221-12/+2
| | | | | | | | | | | VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. llvm-svn: 128103
* Migrate the fix in r128041 to ARM's fastisel support as well.Eric Christopher2011-03-221-13/+18
| | | | | | Fixes rdar://9169640 llvm-svn: 128100
* Change MRC and MRC2 instructions to model the output register properlyBruno Cardoso Lopes2011-03-223-24/+37
| | | | llvm-svn: 128085
* ptx: add analyze/insert/remove branchChe-Liang Chiou2011-03-223-3/+170
| | | | llvm-svn: 128084
* Avoid -Wunused-variable in -asserts buildsMatt Beaumont-Gay2011-03-221-6/+4
| | | | llvm-svn: 128048
* Fix fast-isel address mode folding to avoid folding instructionsDan Gohman2011-03-221-16/+22
| | | | | | outside of the current basic block. This fixes PR9500, rdar://9156159. llvm-svn: 128041
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-2111-19/+36
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* This README entry was fixed recently.Eli Friedman2011-03-211-28/+0
| | | | llvm-svn: 127982
* Re-apply r127953 with fixes: eliminate empty return block if it has no ↵Evan Cheng2011-03-214-0/+27
| | | | | | predecessors; update dominator tree if cfg is modified. llvm-svn: 127981
* Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessorsDaniel Dunbar2011-03-194-27/+0
| | | | | | to canonicalize IR", it broke a lot of things. llvm-svn: 127954
* SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IREvan Cheng2011-03-194-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to have single return block (at least getting there) for optimizations. This is general goodness but it would prevent some tailcall optimizations. One specific case is code like this: int f1(void); int f2(void); int f3(void); int f4(void); int f5(void); int f6(void); int foo(int x) { switch(x) { case 1: return f1(); case 2: return f2(); case 3: return f3(); case 4: return f4(); case 5: return f5(); case 6: return f6(); } } => LBB0_2: ## %sw.bb callq _f1 popq %rbp ret LBB0_3: ## %sw.bb1 callq _f2 popq %rbp ret LBB0_4: ## %sw.bb3 callq _f3 popq %rbp ret This patch teaches codegenprep to duplicate returns when the return value is a phi and where the phi operands are produced by tail calls followed by an unconditional branch: sw.bb7: ; preds = %entry %call8 = tail call i32 @f5() nounwind br label %return sw.bb9: ; preds = %entry %call10 = tail call i32 @f6() nounwind br label %return return: %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ] ret i32 %retval.0 This allows codegen to generate better code like this: LBB0_2: ## %sw.bb jmp _f1 ## TAILCALL LBB0_3: ## %sw.bb1 jmp _f2 ## TAILCALL LBB0_4: ## %sw.bb3 jmp _f3 ## TAILCALL rdar://9147433 llvm-svn: 127953
* Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem2011-03-191-0/+1
| | | | | | | | not have native support for this operation (such as X86). The legalized code uses two vector INT_TO_FP operations and is faster than scalarizing. llvm-svn: 127951
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