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* Turn the EdgeBundles class into a stand-alone machine CFG analysis pass.Jakob Stoklund Olesen2011-01-041-0/+3
| | | | | | | | | | The analysis will be needed by both the greedy register allocator and the X86FloatingPoint pass. It only needs to be computed once when the CFG doesn't change. This pass is very fast, usually showing up as 0.0% wall time. llvm-svn: 122832
* Eliminate a warning compiling with llvm-gcc. (IMO theDale Johannesen2011-01-041-1/+1
| | | | | | warning is overzealous but gcc is what it is.) llvm-svn: 122829
* Fix the ARM IIC_iCMPsi itinerary and add an important assert.Andrew Trick2011-01-042-1/+3
| | | | llvm-svn: 122794
* Formatting changes. No functionality change.Bill Wendling2011-01-031-80/+77
| | | | llvm-svn: 122789
* Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack inEvan Cheng2011-01-032-11/+88
| | | | | | | | | | | prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if the adjustment is 4 in 32-bit mode. In the epilogue, takes care to pop to a caller-saved register that's not live at the exit (either return or tailcall instruction). rdar://8771137 llvm-svn: 122783
* Fix more stack layout issues in the MBlaze backend.Wesley Peck2011-01-033-25/+40
| | | | llvm-svn: 122778
* Try to reuse the value when lowering memset.Benjamin Kramer2011-01-021-44/+0
| | | | | | | | | | This allows us to compile: void test(char *s, int a) { __builtin_memset(s, a, 15); } into 1 mul + 3 stores instead of 3 muls + 3 stores. llvm-svn: 122710
* A workaround for a bug in cmake 2.8.3 diagnosed on PR 8885.Oscar Fuentes2011-01-021-0/+5
| | | | llvm-svn: 122706
* update a bunch of entries.Chris Lattner2011-01-022-137/+56
| | | | llvm-svn: 122700
* Allow loop-idiom to run on multiple BB loops, but still only scan the loop Chris Lattner2011-01-021-8/+0
| | | | | | | | | | | | | | | | | | header for now for memset/memcpy opportunities. It turns out that loop-rotate is successfully rotating loops, but *DOESN'T MERGE THE BLOCKS*, turning "for loops" into 2 basic block loops that loop-idiom was ignoring. With this fix, we form many *many* more memcpy and memsets than before, including on the "history" loops in the viterbi benchmark, which look like this: for (j=0; j<MAX_history; ++j) { history_new[i][j+1] = history[2*i][j]; } Transforming these loops into memcpy's speeds up the viterbi benchmark from 11.98s to 3.55s on my machine. Woo. llvm-svn: 122685
* a missed __builtin_object_size case.Chris Lattner2011-01-011-0/+17
| | | | llvm-svn: 122676
* various updates.Chris Lattner2011-01-011-31/+29
| | | | llvm-svn: 122675
* Add support for the 'H' modifier.Rafael Espindola2011-01-011-0/+6
| | | | llvm-svn: 122667
* Model operand restrictions of mul-like instructions on ARMv5 viaAnton Korobeynikov2011-01-014-10/+100
| | | | | | | | | earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
* Revert commit 122654 at the request of Chris, who reckons that instsimplifyDuncan Sands2011-01-011-0/+11
| | | | | | is the wrong hammer for this nail, and is probably right. llvm-svn: 122661
* Fix a README item by having InstructionSimplify do a mild form of valueDuncan Sands2011-01-011-11/+0
| | | | | | | | | | | numbering, in which it considers (for example) "%a = add i32 %x, %y" and "%b = add i32 %x, %y" to be equal because the operands are equal and the result of the instructions only depends on the values of the operands. This has almost no effect (it removes 4 instructions from gcc-as-one-file), and perhaps slows down compilation: I measured a 0.4% slowdown on the large gcc-as-one-file testcase, but it wasn't statistically significant. llvm-svn: 122654
* ptx: remove reg-reg addressing mode and st.constChe-Liang Chiou2011-01-012-29/+11
| | | | llvm-svn: 122653
* ptx: add store instructionChe-Liang Chiou2011-01-014-4/+101
| | | | llvm-svn: 122652
* Add to the list of cmake files the object file, not the asm file. ThisOscar Fuentes2010-12-311-1/+1
| | | | | | | is necessary for executing the custom command that runs the assember. Fixes PR8877. llvm-svn: 122649
* Add another non-commutable instruction that gas accepts commuted forms for.Nick Lewycky2010-12-301-3/+4
| | | | | | Fixes PR8861. llvm-svn: 122641
* ptx: add state spacesChe-Liang Chiou2010-12-303-8/+63
| | | | llvm-svn: 122638
* Fix stack layout error in MBlaze backend.Wesley Peck2010-12-292-37/+98
| | | | llvm-svn: 122631
* SPARC backend fix: correctly passing arguments through stackVenkatraman Govindaraju2010-12-291-23/+51
| | | | llvm-svn: 122626
* CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some ↵NAKAMURA Takumi2010-12-293-3/+11
| | | | | | files in Target/ARM and Target/X86. llvm-svn: 122623
* Multiple SPARC backend fixes: added Y register; updated select_cc, subx, ↵Venkatraman Govindaraju2010-12-283-21/+35
| | | | | | | | subxcc defs/uses; and fixed CustomInserter. llvm-svn: 122607
* add a note from llvmdevChris Lattner2010-12-281-0/+11
| | | | llvm-svn: 122603
* Add support for the same encodings of the personality function that gnu asRafael Espindola2010-12-271-0/+1
| | | | | | supports. llvm-svn: 122577
* fix some sort of weird pastoChris Lattner2010-12-261-60/+0
| | | | llvm-svn: 122560
* add a noteChris Lattner2010-12-261-0/+91
| | | | llvm-svn: 122559
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-2416-39/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-2411-169/+169
| | | | llvm-svn: 122539
* Use a StringSwitch<> instead of a manually constructed string matcher.Jim Grosbach2010-12-241-10/+7
| | | | llvm-svn: 122530
* Code clean up. No functionality change.Evan Cheng2010-12-231-49/+48
| | | | llvm-svn: 122528
* Remove dead patterns.Jim Grosbach2010-12-231-26/+0
| | | | llvm-svn: 122524
* Recognize a few more documented register name aliases for ARM in the asm lexer.Jim Grosbach2010-12-231-0/+18
| | | | llvm-svn: 122523
* Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.Bob Wilson2010-12-231-0/+3
| | | | | | | | If the basic block containing the BCCi64 (or BCCZi64) instruction ends with an unconditional branch, that branch needs to be deleted before appending the expansion of the BCCi64 to the end of the block. llvm-svn: 122521
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-2316-101/+101
| | | | llvm-svn: 122513
* flags -> glue for selectiondagChris Lattner2010-12-231-2/+2
| | | | llvm-svn: 122509
* Remove/fix invalid README entries. The well thought out strcpy function ↵Benjamin Kramer2010-12-231-21/+2
| | | | | | doesn't return a pointer to the end of the string. llvm-svn: 122496
* Remove some obsolete README items, add a new one off the top of my head.Benjamin Kramer2010-12-231-78/+26
| | | | llvm-svn: 122495
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-232-2/+1
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* Trailing whitespace.Jim Grosbach2010-12-221-15/+15
| | | | llvm-svn: 122456
* X86: Lower a select directly to a setcc_carry if possible.Benjamin Kramer2010-12-222-52/+17
| | | | | | | | | | | | | | | | | | int test(unsigned long a, unsigned long b) { return -(a < b); } compiles to _test: ## @test cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7] sbbl %eax, %eax ## encoding: [0x19,0xc0] ret ## encoding: [0xc3] instead of _test: ## @test xorl %ecx, %ecx ## encoding: [0x31,0xc9] cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7] movl $-1, %eax ## encoding: [0xb8,0xff,0xff,0xff,0xff] cmovael %ecx, %eax ## encoding: [0x0f,0x43,0xc1] ret ## encoding: [0xc3] llvm-svn: 122451
* ptx: add ld instruction and testChe-Liang Chiou2010-12-226-22/+181
| | | | llvm-svn: 122398
* Don't generate carry bit when loading immediate values on the Microblaze.Wesley Peck2010-12-222-2/+2
| | | | llvm-svn: 122385
* Add support for some of the LLVM atomic operations to the MBlaze backend.Wesley Peck2010-12-223-156/+386
| | | | llvm-svn: 122384
* Modeling the carry bit in the MSR register of the MicroBlaze.Wesley Peck2010-12-223-83/+140
| | | | llvm-svn: 122381
* Fix a regression introduced into the MBlaze delay slot filler.Wesley Peck2010-12-221-6/+25
| | | | llvm-svn: 122379
* Add some x86 specific dagcombines for conditional increments.Benjamin Kramer2010-12-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (add Y, (sete X, 0)) -> cmp X, 1; adc 0, Y (add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y (sub (sete X, 0), Y) -> cmp X, 1; sbb 0, Y (sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y for unsigned foo(unsigned a, unsigned b) { if (a == 0) b++; return b; } we now get: foo: cmpl $1, %edi movl %esi, %eax adcl $0, %eax ret instead of: foo: testl %edi, %edi sete %al movzbl %al, %eax addl %esi, %eax ret llvm-svn: 122364
* Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.Bob Wilson2010-12-211-5/+103
| | | | | | | | | | | Type legalization splits up i64 values into pairs of i32 values, which leads to poor quality code when inserting or extracting i64 vector elements. If the vector element is loaded or stored, it can be treated as an f64 value and loaded or stored directly from a VPR register. Use the pre-legalization DAG combiner to cast those vector elements to f64 types so that the type legalizer won't mess them up. Radar 8755338. llvm-svn: 122319
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