summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.Daniel Dunbar2010-12-163-4/+17
| | | | llvm-svn: 121973
* Fix indentation (per style guide).Daniel Dunbar2010-12-161-49/+49
| | | | llvm-svn: 121972
* MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.Daniel Dunbar2010-12-163-0/+3
| | | | llvm-svn: 121971
* MC: Move target specific fixup info descriptors to TargetAsmBackend instead ofDaniel Dunbar2010-12-169-84/+89
| | | | | | | the MCCodeEmitter, which seems like a better organization. - Also, cleaned up some magic constants while in the area. llvm-svn: 121953
* MC: Make TargetAsmBackend available to the AsmStreamer.Daniel Dunbar2010-12-162-1/+3
| | | | | | - Treaty talks on the non-proliferation of MC objects broke down. llvm-svn: 121949
* Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by ClangMatt Beaumont-Gay2010-12-161-1/+1
| | | | | | (see PR4579). llvm-svn: 121939
* Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff forBill Wendling2010-12-163-18/+1
| | | | | | it. I.e., it was always an immediate value. llvm-svn: 121932
* Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRiBill Wendling2010-12-161-0/+2
| | | | | | | | | respectively. It may be a bug that these opcodes are getting this far into machine code generation. llvm-svn: 121931
* Add encodings for Thumb1 Spill and Restore pseudos.Bill Wendling2010-12-161-2/+12
| | | | llvm-svn: 121929
* Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach2010-12-154-16/+2
| | | | | | Canonicalize on tLDRpci and remove tLDRcp. llvm-svn: 121920
* Don't handle -arm-long-calls in fast isel for now.Eric Christopher2010-12-152-1/+9
| | | | llvm-svn: 121919
* If we're changing the frame register to a physical register other than SP, weBill Wendling2010-12-152-29/+38
| | | | | | need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively. llvm-svn: 121915
* Whitespace cleanups.Bill Wendling2010-12-151-3/+3
| | | | llvm-svn: 121914
* Only rr forms of ADD*_DB are commutable.Evan Cheng2010-12-151-1/+3
| | | | llvm-svn: 121908
* Add Neon VCVT instructions for f32 <-> f16 conversions.Bob Wilson2010-12-153-1/+22
| | | | | | | Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. llvm-svn: 121902
* Lower the MBlaze target specific calling conventions for "interrupt_handler"Wesley Peck2010-12-154-12/+119
| | | | | | | and "save_volatiles" correctly. This completes the custom calling convention functionality changes for the MBlaze backend that were started in 121888. llvm-svn: 121891
* Add some special purpose register definitions to the MBlaze backend and ↵Wesley Peck2010-12-151-80/+34
| | | | | | cleanup some old, unused floating point register definitions. llvm-svn: 121882
* Tweak a few pseudo-inst pattern base classes.Jim Grosbach2010-12-151-4/+4
| | | | llvm-svn: 121878
* The new t2LEApcrel* pseudo instructions need the size specified.Jim Grosbach2010-12-152-5/+13
| | | | | | rdar://8768390 llvm-svn: 121876
* Implement cleanups suggested by Daniel.Owen Anderson2010-12-151-4/+4
| | | | llvm-svn: 121875
* Add fixups for Thumb LDR/STR instructions.Bill Wendling2010-12-153-3/+20
| | | | llvm-svn: 121858
* add another overflow idiomChris Lattner2010-12-151-0/+8
| | | | llvm-svn: 121854
* add a note about overflow idiom recognition.Chris Lattner2010-12-151-1/+19
| | | | llvm-svn: 121853
* add a shift/imul missed optimizationChris Lattner2010-12-151-0/+45
| | | | llvm-svn: 121850
* add a note about a SPEC hack that gcc mainline does.Chris Lattner2010-12-151-0/+23
| | | | llvm-svn: 121849
* Reapply r121808 now that the missing patterns have been supplied.Bill Wendling2010-12-151-16/+21
| | | | llvm-svn: 121820
* Add some missing patterns now that tLDRB and tLDRH are split into reg andBill Wendling2010-12-151-2/+12
| | | | | | immediate versions. llvm-svn: 121819
* Revert r121808 until I can fix the build.Bill Wendling2010-12-151-21/+16
| | | | llvm-svn: 121815
* thumb adr fixup needs alignment just like the t2 version.Jim Grosbach2010-12-141-1/+2
| | | | llvm-svn: 121812
* Comments and cleaning.Bill Wendling2010-12-141-6/+4
| | | | llvm-svn: 121809
* Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. InBill Wendling2010-12-141-16/+21
| | | | | | | | | | | | | | | | particular, we want ldr r2, [r3] to be equivalent to ldr r2, [r3, #0] and not ldr r2, [r3, r0] llvm-svn: 121808
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-146-21/+50
| | | | llvm-svn: 121798
* Fix comment.Bill Wendling2010-12-141-1/+1
| | | | llvm-svn: 121797
* Multiclassify the LDR/STR encoding patterns. The only functionality differenceBill Wendling2010-12-141-69/+69
| | | | | | | is the addition of the FoldableAsLoad & Rematerializable flags to some of the load instructions. ARM has these flags set for them. llvm-svn: 121794
* trailing whitespaceJim Grosbach2010-12-141-4/+4
| | | | llvm-svn: 121792
* Refactor a bit for legibility.Jim Grosbach2010-12-141-28/+27
| | | | llvm-svn: 121790
* trailing whitespace.Jim Grosbach2010-12-141-4/+4
| | | | llvm-svn: 121789
* Make sure to propagate the predicate operands for LEApcrel to ADR.Jim Grosbach2010-12-141-4/+4
| | | | llvm-svn: 121788
* Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.Owen Anderson2010-12-141-1/+1
| | | | llvm-svn: 121784
* Add TargetRegisterInfo::printReg() to pretty-print registers.Jakob Stoklund Olesen2010-12-141-0/+8
| | | | llvm-svn: 121780
* MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.Daniel Dunbar2010-12-141-1/+1
| | | | llvm-svn: 121772
* Trailing whitespaceJim Grosbach2010-12-141-6/+6
| | | | llvm-svn: 121769
* Use the integer scheduling intrinsic for integer loads and stores.Bill Wendling2010-12-141-6/+6
| | | | llvm-svn: 121765
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-1410-224/+340
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663Evan Cheng2010-12-141-0/+20
| | | | llvm-svn: 121746
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ↵Owen Anderson2010-12-146-19/+74
| | | | | | | | much later, which makes the entire process cleaner. llvm-svn: 121735
* Remove the rest of the *_sfp Neon instruction patterns.Bob Wilson2010-12-132-82/+32
| | | | | | | | | | | | | Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions. This change made a big difference in the code generated for the CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing a fine job, but some instructions that were previously moved outside the loop are not moved now. It's using fewer VFP registers now, which is generally a good thing, so I think the estimates for register pressure changed and that affected the LICM behavior. Since that isn't obviously wrong, I've just changed the test file. This completes the work for Radar 8711675. llvm-svn: 121730
* Simplify N2VSPat, removing some unnecessary type arguments.Bob Wilson2010-12-131-13/+12
| | | | llvm-svn: 121729
* Revert r121721, which broke buildbots.Owen Anderson2010-12-137-85/+21
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-137-21/+85
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
OpenPOWER on IntegriCloud