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* [ms-inline asm] Make the comment a bit more verbose.Chad Rosier2013-02-201-2/+6
| | | | llvm-svn: 175641
* Fix bug 14779 for passing anonymous aggregates [patch by Kai Nacke].Bill Schmidt2013-02-201-1/+7
| | | | | | | | The PPC backend doesn't handle these correctly. This patch uses logic similar to that in the X86 and ARM backends to track these arguments properly. llvm-svn: 175635
* Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.Jyotsna Verma2013-02-2010-32/+336
| | | | | | | | Add HexagonMCInst class which adds various Hexagon VLIW annotations. In addition, this class also includes some APIs related to the constant extenders. llvm-svn: 175634
* Fix PR15155: lost vadd/vsplat optimization.Bill Schmidt2013-02-203-8/+43
| | | | | | | | | | | | | | During lowering of a BUILD_VECTOR, we look for opportunities to use a vector splat. When the splatted value fits in 5 signed bits, a single splat does the job. When it doesn't fit in 5 bits but does fit in 6, and is an even value, we can splat on half the value and add the result to itself. This last optimization hasn't been working recently because of improved constant folding. To circumvent this, create a pseudo VADD_SPLAT that can be expanded during instruction selection. llvm-svn: 175632
* I optimized the following patterns:Elena Demikhovsky2013-02-202-0/+40
| | | | | | | | | | | | | | | | sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619
* Fix thumbv5e frame lowering assertion failure.Logan Chien2013-02-201-3/+6
| | | | | | | | | | | | | | It is possible that frame pointer is not found in the callee saved info, thus FramePtrSpillFI may be incorrect if we don't check the result of hasFP(MF). Besides, if we enable the stack coloring algorithm, there will be an assertion to ensure the slot is live. But in the test case, %var1 is not live in the prologue of the function, and we will get the assertion failure. Note: There is similar code in ARMFrameLowering.cpp. llvm-svn: 175616
* Fix the (clang -Werror) build by removing an unused member variable.David Blaikie2013-02-201-2/+1
| | | | llvm-svn: 175607
* Expand pseudos/macros:Reed Kotler2013-02-203-10/+110
| | | | | | | | SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. llvm-svn: 175593
* Add missing #include.Jakub Staszak2013-02-201-0/+1
| | | | llvm-svn: 175583
* [ms-inline asm] Force the use of a base pointer if the MachineFunction includesChad Rosier2013-02-191-2/+4
| | | | | | | | | | | | | MS-style inline assembly. This is a follow-on to r175334. Forcing a FP to be emitted doesn't ensure it will be used. Therefore, force the base pointer as well. We now treat MS inline assembly in the same way we treat functions with dynamic stack realignment and VLAs. This guarantees the BP will be used to reference parameters and locals. rdar://13218191 llvm-svn: 175576
* ELF symbol table field st_other support, Jack Carter2013-02-191-0/+4
| | | | | | | | | | | | excluding visibility bits. Mips (o32 abi) specific e_header setting. EF_MIPS_ABI_O32 needs to be set in the ELF header flags for o32 abi output. Contributer: Reed Kotler llvm-svn: 175569
* ELF symbol table field st_other support, Jack Carter2013-02-191-1/+4
| | | | | | | | | | | | excluding visibility bits. Mips (Mips16) specific e_header setting. EF_MIPS_ARCH_ASE_M16 needs to be set in the ELF header flags for Mips16. Contributer: Reed Kotler llvm-svn: 175566
* ELF symbol table field st_other support, Jack Carter2013-02-194-6/+36
| | | | | | | | | | | excluding visibility bits. Mips (MicroMips) specific STO handling . The st_other field settig for STO_MIPS_MICROMIPS Contributer: Zoran Jovanovic llvm-svn: 175564
* Add obvious constantness.Jakub Staszak2013-02-191-2/+2
| | | | llvm-svn: 175560
* ARM NEON: Don't need COPY_TO_REGCLASS in patternArnold Schwaighofer2013-02-191-3/+1
| | | | | | | | | | | | | | | | | In my previous commit: "Merge a f32 bitcast of a v2i32 extractelt A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers." I added a pattern containing a copy_to_regclass. The copy_to_regclass is actually not needed. radar://13191881 llvm-svn: 175555
* ARM: Allocation hints must make sure to be in the alloc order.Jim Grosbach2013-02-191-1/+2
| | | | | | | | | When creating an allocation hint for a register pair, make sure the hint for the physical register reference is still in the allocation order. rdar://13240556 llvm-svn: 175541
* Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h withJyotsna Verma2013-02-191-28/+60
| | | | | | HexagonInstrFormats.td. llvm-svn: 175537
* Clean up HiPE prologue emission a bit and avoid signed arithmetic tricks.Benjamin Kramer2013-02-191-43/+47
| | | | | | No intended functionality change. llvm-svn: 175536
* Move LLVM_LIBRARY_VISIBILITY for consistency with what was done toRafael Espindola2013-02-191-1/+1
| | | | | | PPCJITInfo.cpp in r175394. llvm-svn: 175531
* Make ARMAsmPrinter pass name more precise and fix comment.Eli Bendersky2013-02-191-6/+2
| | | | llvm-svn: 175527
* Make pass name more precise and fix comment.Eli Bendersky2013-02-191-6/+2
| | | | llvm-svn: 175525
* ARM NEON: Merge a f32 bitcast of a v2i32 extracteltArnold Schwaighofer2013-02-191-0/+6
| | | | | | | | | | | | | | A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 llvm-svn: 175520
* R600: Add AR_X to the R600_TReg_X register class.Tom Stellard2013-02-191-1/+1
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175519
* R600: Mark all members of the TRegMem register class as reservedTom Stellard2013-02-191-0/+6
| | | | | | | | This stops the Machine Verifier from complaining about uses of undefined physical registers. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175518
* R600: Fix scheduler crash caused by invalid MachinePointerInfoTom Stellard2013-02-191-1/+1
| | | | | | | | | | | | | | Kernel function arguments are lowered to loads from the PARAM_I address space. When creating these load instructions, we were initializing their MachinePointerInfo with an Arguement object that was not attached to any function. This was causing the MachineScheduler to crash when it tried to access the parent of the Arguement. This has been fixed by initializing the MachinePointerInfo with a UndefValue instead. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175517
* R600: Fix tracking of implicit defs in the IndirectAddressing passTom Stellard2013-02-191-7/+25
| | | | | | | | | In some cases, we were losing track of live implicit registers which was creating dead defs and causing the scheduler to produce invalid code. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175516
* Fix capitalization in comment to match function name.Craig Topper2013-02-191-1/+1
| | | | llvm-svn: 175497
* Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler2013-02-192-1/+48
| | | | | | BtnezT8SltiX16, BtnezT8SltiuX16 . llvm-svn: 175486
* Remove some unused private fields from the AArch64MCCodeEmitter. TheseChandler Carruth2013-02-191-7/+2
| | | | | | | | | | fields were only ever set in the constructor. The create method retains its consistent interface so that these bits can be re-threaded through the emitter if they're ever needed. This was found by the -Wunused-private-field Clang warning. llvm-svn: 175482
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-193-0/+58
| | | | llvm-svn: 175474
* Use array_pod_sort instead of std::sort.Jakub Staszak2013-02-181-2/+2
| | | | llvm-svn: 175472
* X86FrameLowering.cpp: Fixup. Sorry for the breakage.NAKAMURA Takumi2013-02-181-1/+1
| | | | llvm-svn: 175467
* Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.David Blaikie2013-02-183-6/+6
| | | | | | | Also removes some redundant DNI comments on function declarations already using the macro. llvm-svn: 175466
* X86FrameLowering.cpp: Fix a warning in -Asserts. [-Wunused-variable]NAKAMURA Takumi2013-02-181-2/+1
| | | | llvm-svn: 175464
* Remove a useless assert.Chad Rosier2013-02-181-1/+0
| | | | llvm-svn: 175463
* [fast-isel] Remove an invalid assert.Chad Rosier2013-02-181-1/+0
| | | | | | | | If the memcpy has an odd length with an alignment of 2, this would incorrectly assert on the last 1 byte copy. rdar://13202135 llvm-svn: 175459
* Fix a 32/64 bit incompatibility in the HiPE prologue generation.Benjamin Kramer2013-02-181-1/+1
| | | | llvm-svn: 175458
* Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.Benjamin Kramer2013-02-182-5/+157
| | | | llvm-svn: 175457
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-187-23/+15
| | | | llvm-svn: 175446
* R600: Support for TBOVincent Lejeune2013-02-183-1/+58
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175445
* R600: Increase number of ArrayBase Reg to 32Vincent Lejeune2013-02-181-2/+2
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175443
* Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler2013-02-181-0/+8
| | | | llvm-svn: 175420
* Expand pseudo/macro BteqzT8SltuX16 . There is no test case becauseReed Kotler2013-02-182-0/+7
| | | | | | | | at this time, llvm is generating a different but equivalent pattern that would lead to this instruction. I am trying to think of a way to get it to generate this. If I can't, I may just remove the pseudo. llvm-svn: 175419
* Expand pseudo/macro BteqzT8SltX16.Reed Kotler2013-02-181-0/+3
| | | | llvm-svn: 175417
* Expand macro/pseudo BteqzT8CmpX16.Reed Kotler2013-02-181-0/+3
| | | | llvm-svn: 175416
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-183-3/+34
| | | | | | | | | | This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. llvm-svn: 175413
* X86: Add a note.Benjamin Kramer2013-02-171-0/+9
| | | | llvm-svn: 175408
* [XCore] Add missing 2r instructions.Richard Osborne2013-02-173-1/+35
| | | | | | | These instructions are not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175407
* [XCore] Add TSETR instruction.Richard Osborne2013-02-173-1/+34
| | | | | | | This instruction is not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175406
* [XCore] Add missing u10 / lu10 instructions.Richard Osborne2013-02-171-1/+12
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175404
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