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* [X86][SSE] Lower vXi8 general shifts to SSE shifts directly. NFCI.Simon Pilgrim2018-08-211-26/+17
| | | | | | Most of these shifts are extended to vXi16 so we don't gain anything from forcing another round of generic shift lowering - we know these extended cases are legal constant splat shifts. llvm-svn: 340307
* [X86][SSE] Lower v8i16 general shifts to SSE shifts directly. NFCI.Simon Pilgrim2018-08-211-9/+9
| | | | | | We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts. llvm-svn: 340302
* [X86][SSE] Lower directly to SSE shifts in the BLEND(SHIFT, SHIFT) combine. ↵Simon Pilgrim2018-08-211-9/+13
| | | | | | | | NFCI. We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts. llvm-svn: 340300
* [AMDGPU] Support idot2 pattern.Farhana Aleen2018-08-212-0/+23
| | | | | | | | | | | | | | | | Summary: Transform add (mul ((i32)S0.x, (i32)S1.x), add( mul ((i32)S0.y, (i32)S1.y), (i32)S3) => i/udot2((v2i16)S0, (v2i16)S1, (i32)S3) Author: FarhanaAleen Reviewed By: arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D50024 llvm-svn: 340295
* [X86][SSE] Add helper function to convert to/between the SSE vector shift ↵Simon Pilgrim2018-08-211-36/+33
| | | | | | | | opcodes. NFCI. Also remove some more getOpcode calls from LowerShift when we already have Opc. llvm-svn: 340290
* [aarch64][mc] Don't lookup symbols when there is no symbol lookup callbackDaniel Sanders2018-08-211-0/+2
| | | | | | | | | | | | | | Summary: When run under llvm-mc-disassemble-fuzzer, there is no symbol lookup callback so tryAddingSymbolicOperand() must fail gracefully instead of crashing Reviewers: aemerson, javed.absar Reviewed By: aemerson Subscribers: lhames, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D51005 llvm-svn: 340287
* [AMDGPU] Allow int types for MUBUF vdataTim Renouf2018-08-211-0/+20
| | | | | | | | | | | | | | | | | Summary: Previously the new llvm.amdgcn.raw/struct.buffer.load/store intrinsics only allowed float types for the data to be loaded or stored, which sometimes meant the frontend needed to generate a bitcast. In this, the new intrinsics copied the old buffer intrinsics. This commit extends the new intrinsics to allow int types as well. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D50315 Change-Id: I8202af2d036455553681dcbb3d7d32ae273f8f85 llvm-svn: 340270
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-217-179/+502
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.buffer.load llvm.amdgcn.raw.buffer.load.format llvm.amdgcn.raw.buffer.load.format.d16 llvm.amdgcn.struct.buffer.load llvm.amdgcn.struct.buffer.load.format llvm.amdgcn.struct.buffer.load.format.d16 llvm.amdgcn.raw.buffer.store llvm.amdgcn.raw.buffer.store.format llvm.amdgcn.raw.buffer.store.format.d16 llvm.amdgcn.struct.buffer.store llvm.amdgcn.struct.buffer.store.format llvm.amdgcn.struct.buffer.store.format.d16 llvm.amdgcn.raw.buffer.atomic.* llvm.amdgcn.struct.buffer.atomic.* with the following changes from the llvm.amdgcn.buffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::BUFFER_* SD nodes always have an index operand, all three offset operands, combined cachepolicy operand, and an extra idxen operand. The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50306 Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205 llvm-svn: 340269
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-217-104/+309
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.tbuffer.load llvm.amdgcn.struct.tbuffer.load llvm.amdgcn.raw.tbuffer.store llvm.amdgcn.struct.tbuffer.store with the following changes from the llvm.amdgcn.tbuffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined format arg (dfmt+nfmt) * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::TBUFFER_* SD nodes always have an index operand, all three offset operands, combined format operand, combined cachepolicy operand, and an extra idxen operand. The tbuffer pseudo- and real instructions now also have a combined format operand. The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store intrinsics continue to work. V2: Separate raw and struct intrinsics. V3: Moved extract_glc and extract_slc defs to a more sensible place. V4: Rebased on D49995. V5: Only two separate offset args instead of three. V6: Pseudo- and real instructions have joint format operand. V7: Restored optionality of dfmt and nfmt in assembler. V8: Addressed minor review comments. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49026 Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4 llvm-svn: 340268
* [MIPS GlobalISel] Select bitwise instructionsPetar Jovanovic2018-08-212-0/+9
| | | | | | | | | | Select bitwise instructions for i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D50183 llvm-svn: 340258
* [WebAssembly] Revert type of wake count in atomic.wake to i32Heejin Ahn2018-08-201-18/+18
| | | | | | | | | | | | | | Summary: We decided to revert this from i64 to i32 in Nov 28 CG meeting. Fixes PR38632. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D51010 llvm-svn: 340234
* [WebAssembly] Remove an unused argument from writeSPToMemory (NFC)Heejin Ahn2018-08-201-8/+5
| | | | | | | | | | Reviewers: dschuff Subscribers: dschuff, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50933 llvm-svn: 340230
* [X86] Prevent lowerVectorShuffleByMerging128BitLanes from creating cyclesCraig Topper2018-08-201-0/+12
| | | | | | | | | | | | Due to some splat handling code in getVectorShuffle, its possible for NewV1/NewV2 to have their mask modified from what is requested. This can lead to cycles being created in the DAG. This patch examines the returned mask and makes sure its different. Long term we may need to look closer at that splat code in getVectorShuffle, or add more splat awareness to getVectorShuffle. Fixes PR38639 Differential Revision: https://reviews.llvm.org/D50981 llvm-svn: 340214
* [X86] Teach combineTruncatedArithmetic to handle some cases of ISD::SUBCraig Topper2018-08-201-26/+21
| | | | | | | | We can safely avoid interfering with the subus combine if both inputs are freely truncatable. Either both extends, or an extend and a constant vector. Differential Revision: https://reviews.llvm.org/D50878 llvm-svn: 340212
* Revert "AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space"Vitaly Buka2018-08-202-2/+2
| | | | | | | | As it introduces out of bound access. This reverts commit r340172 and r340171 llvm-svn: 340202
* [PSV] Update API to be able to use TargetCustom without UB.Marcello Maggioni2018-08-204-4/+4
| | | | | | | | | | | getTargetCustom() requires values for "Kind" in the constructor that are not in the PSVKind enum. Passing a value that is not inside an enum as an argument to a constructor of the type of the enum is UB. Changing to the underlying type of the enum would solve the UB Differential Revision: https://reviews.llvm.org/D50909 llvm-svn: 340200
* AMDGPU: fix compilation errors since r340171Samuel Pitoiset2018-08-201-1/+1
| | | | | | | Some buildbot slaves reports compilation errors, but it compiled fine on my side, sorry for the breakage. llvm-svn: 340172
* AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr spaceSamuel Pitoiset2018-08-202-2/+2
| | | | | | | | | | | | | | 32-bit constant address space is declared as 6, so the maximum number of address spaces is 6, not 5. Fixes "LLVM ERROR: Pointer address space out of range". v3: use static_assert() v2: add a very simple test for 32-bit addr space Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106630 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> llvm-svn: 340171
* [AArch64][SVE] Asm: Add SVE System registersSander de Smalen2018-08-201-0/+15
| | | | | | | | | | | | | | | | | | This patch adds system registers for controlling aspects of SVE: - ZCR_EL1 (r/w) visible at EL1 and EL0. - ZCR_EL2 (r/w) visible at EL2 and Non-secure EL1 and EL0. - ZCR_EL3 (r/w) visible at all exception levels. and a system register identifying SVE: - ID_AA64ZFR0_EL1 (r) SVE Feature identifier. Reviewers: SjoerdMeijer, samparker, pbarrio, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D50885 llvm-svn: 340158
* [PowerPC] Add a peephole post RA to transform the inst that fed by addQingShan Zhang2018-08-202-50/+353
| | | | | | | | | | | | | If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149
* [X86] Fix an issue in the matching for ADDUS.Craig Topper2018-08-191-12/+11
| | | | | | | | We were basically assuming only one operand of the compare could be an ADD node and using that to swap operands. But we can have a normal add followed by a saturing add. This rewrites the canonicalization to just be based on the condition code. llvm-svn: 340134
* [X86] Use SDValue::operator== instead of DAG.isEqualTo in strictly integer ↵Craig Topper2018-08-181-2/+2
| | | | | | | | matching. isEqualTo is more useful for floating point. operator== is sufficient for integer. llvm-svn: 340130
* [X86] Simplify the PADDUS legality check in combineSelect to match PSUBUS. NFCCraig Topper2018-08-181-4/+5
| | | | | | While there remove some trailing whitespace. llvm-svn: 340129
* [X86] Add support for using 512-bit PSUBUS to combineSelect.Craig Topper2018-08-181-5/+8
| | | | | | | | The code already support 128 and 256 and even knows to split 256 for AVX1. So we really just needed to stop looking for specific VTs and subtarget features and just look for legal VTs with i8/i16 elements. While there, add some curly braces around outer if statement bodies that contain only another if. It makes all the closing curly braces look more regular. llvm-svn: 340128
* [X86] Replace all single match schedule class instregexs with instrs entriesSimon Pilgrim2018-08-186-475/+455
| | | | | | Helps reduce cost of instrw collection llvm-svn: 340124
* [X86] Merge shift/rotate schedule class instregexsSimon Pilgrim2018-08-185-102/+51
| | | | | | Helps reduce cost of instrw collection llvm-svn: 340123
* Add the extended XMM registers mappings for AVX-512.Zachary Turner2018-08-181-0/+17
| | | | | | | After this we should have the entire AVX-512 register set mapping in place. llvm-svn: 340118
* [X86] Remove detectAddSubSatPattern.Craig Topper2018-08-171-115/+0
| | | | | | This was added very recently in r339650, but appears to be completely untested and has at least one bug in it. llvm-svn: 340086
* [Hexagon] Remove unused functions from HexagonInstPrinter, NFCKrzysztof Parzyszek2018-08-172-124/+8
| | | | llvm-svn: 340081
* [X86][SSE] Lower constant vXi8 ISD::SRL/ISD::SRA using PMULLWSimon Pilgrim2018-08-171-3/+52
| | | | | | | | Extending the concept introduced in D49562, this patch lowers constant vXi8 ISD::SRL/ISD::SRA by zero/sign extending to vXi16 and using PMULLW and then truncating the high 8 bits of the result. Differential Revision: https://reviews.llvm.org/D50781 llvm-svn: 340062
* [X86] Use hasOneUse instead of isOnlyUserOf. NFCICraig Topper2018-08-171-1/+1
| | | | | | isOnlyUserOf is a little heavier because it allows the node to be used multiple times by the other node. In this case we are looking at a truncate which only has one operand so we know it can only use it once. Thus hasOneUse is better. llvm-svn: 340059
* [PowerPC] Generate lxsd instead of the ld->mtvsrd sequence for vector loadsStefan Pintilie2018-08-171-0/+29
| | | | | | | | | | | | | | | | | | This patch addresses: - Implementation within PPCISelLowering.cpp to check if we should use direct load into vector instructions (such as lxsd/lfd ) when the scalar_to_vector function is used; which will allow us to catch as many cases of the scalar_to_vector uses as possible to translate the ld->mtvsrd sequence into lxsd. - Test cases to exhibit the behaviour of emitting lxsd/lfd. Patch by amyk Differential revision: https://reviews.llvm.org/D49698 llvm-svn: 340037
* [X86] Fix liveness information when expanding X86::EH_SjLj_LongJmp64Francis Visoiu Mistrih2018-08-171-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | test/CodeGen/X86/shadow-stack.ll has the following machine verifier errors: ``` *** Bad machine code: Using a killed virtual register *** - function: bar - basic block: %bb.6 entry (0x7fdc81857818) - instruction: %3:gr64 = MOV64rm killed %2:gr64, 1, $noreg, 8, $noreg - operand 1: killed %2:gr64 *** Bad machine code: Using a killed virtual register *** - function: bar - basic block: %bb.6 entry (0x7fdc81857818) - instruction: $rsp = MOV64rm killed %2:gr64, 1, $noreg, 16, $noreg - operand 1: killed %2:gr64 *** Bad machine code: Virtual register killed in block, but needed live out. *** - function: bar - basic block: %bb.2 entry (0x7fdc818574f8) Virtual register %2 is used after the block. ``` The fix here is to only copy the machine operand's register without the kill flags for all the instructions except the very last one of the sequence. I had to insert dummy PHIs in the test case to force the NoPHI function property to be set to false. More on this here: https://llvm.org/PR38439 Differential Revision: https://reviews.llvm.org/D50260 llvm-svn: 340033
* [Hexagon] Expand vgather pseudos during packetizationKrzysztof Parzyszek2018-08-177-209/+123
| | | | | | This will allow packetizing the vgather expansion with other instructions. llvm-svn: 340028
* [RISCV] Remove unused functionRoger Ferrer Ibanez2018-08-172-21/+0
| | | | | | | | | | | This function is not virtual, it is private and it is not called anywhere. No regression is introduced by removing it. I think we can safely remove it. Differential Revision: https://reviews.llvm.org/D50836 llvm-svn: 340024
* [AArch64] - Generate pointer authentication instructionsLuke Cheeseman2018-08-171-0/+59
| | | | | | | | | | | | | | | | - Generate pointer authentication instructions - The functions instrumented depend on function attribtues: all (all functions instrumentent) non-leaf (only those that spill LR) none - Function epilogues sign the LR before spilling to the stack and authenticate the LR once restored - If the target is v8.3a or greater than can use the combined authenticate and return instruction Differential revision: https://reviews.llvm.org/D49793 llvm-svn: 340018
* [PowerPC] Generate Power9 extswsli extend sign and shift immediate instructionNemanja Ivanovic2018-08-174-3/+38
| | | | | | | | | | | Add a DAG combine for the PowerPC code generator to generate the Power9 extswsli extend sign and shift immediate instruction. Patch by RolandF. Differential revision: https://reviews.llvm.org/D49879 llvm-svn: 340016
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-1711-3/+142
| | | | | | | | | | | | | | | | | | Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 llvm-svn: 340013
* [Sparc] Get sret arg size from CallLoweringInfo.getArgs()Daniel Cederman2018-08-172-47/+6
| | | | | | | | | | | | | | | | | | | | Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
* [Sparc] Flush register windows for @llvm.returnaddress(1)Daniel Cederman2018-08-171-11/+6
| | | | | | | | | | | | | | | | | | Summary: When @llvm.returnaddress is called with a value higher than 0 it needs to read from the call stack to get the return address. This means that the register windows needs to be flushed to the stack to guarantee that the data read is valid. For values higher than 1 this is done indirectly by the call to getFRAMEADDR(), but not for the value 1. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48636 llvm-svn: 340003
* [ARM][NFC] ARMCodeGenPrepare: some refactoring and algorithm descriptionSjoerd Meijer2018-08-171-33/+85
| | | | | | Differential Revision: https://reviews.llvm.org/D50846 llvm-svn: 339997
* [WebAssembly] Modify LateEHPrepare one-line description (NFC)Heejin Ahn2018-08-171-1/+1
| | | | llvm-svn: 339972
* [WebAssembly] CFG stackify support for exception handlingHeejin Ahn2018-08-161-108/+542
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds support for exception handling to CFGStackify pass. This only adds TRY / END_TRY markers and DOES NOT yet fix unwind mismatches that can be created by the linearization of the CFG into the structural wasm format. The mismatch fix will be added by following patches. In detail, this patch - Added support for TRY / END_TRY markers to support EH - Changed many static functions into class member functions as they take too many arguments now - Added several more bookeeping data structures - Refactored routines that decide where to insert markers, because without refactoring this got too complicated as we added support for new kinds of markers (TRY/END_TRY). - Rewrote rethrow instructions' BB arguments to relative depths in EH pad stack. Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D48273 llvm-svn: 339967
* [X86] In EFLAGS copy pass, don't emit EXTRACT_SUBREG instructions since ↵Craig Topper2018-08-161-6/+11
| | | | | | | | | | | | | | we're after peephole Normally the peephole pass converts EXTRACT_SUBREG to COPY instructions. But we're after peephole so we can't rely on it to clean these up. To fix this, the eflags pass now emits a COPY with a subreg input. I also noticed that in 32-bit mode we need to constrain the input to the copy to ensure the subreg is valid. Otherwise we'll fail verify-machineinstrs Differential Revision: https://reviews.llvm.org/D50656 llvm-svn: 339945
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-1627-241/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a generically extensible collection of extra info attached to a `MachineInstr`. The primary change here is cleaning up the APIs used for setting and manipulating the `MachineMemOperand` pointer arrays so chat we can change how they are allocated. Then we introduce an extra info object that using the trailing object pattern to attach some number of MMOs but also other extra info. The design of this is specifically so that this extra info has a fixed necessary cost (the header tracking what extra info is included) and everything else can be tail allocated. This pattern works especially well with a `BumpPtrAllocator` which we use here. I've also added the basic scaffolding for putting interesting pointers into this, namely pre- and post-instruction symbols. These aren't used anywhere yet, they're just there to ensure I've actually gotten the data structure types correct. I'll flesh out support for these in a subsequent patch (MIR dumping, parsing, the works). Finally, I've included an optimization where we store any single pointer inline in the `MachineInstr` to avoid the allocation overhead. This is expected to be the overwhelmingly most common case and so should avoid any memory usage growth due to slightly less clever / dense allocation when dealing with >1 MMO. This did require several ergonomic improvements to the `PointerSumType` to reasonably support the various usage models. This also has a side effect of freeing up 8 bits within the `MachineInstr` which could be repurposed for something else. The suggested direction here came largely from Hal Finkel. I hope it was worth it. ;] It does hopefully clear a path for subsequent extensions w/o nearly as much leg work. Lots of thanks to Reid and Justin for careful reviews and ideas about how to do all of this. Differential Revision: https://reviews.llvm.org/D50701 llvm-svn: 339940
* [WebAssembly] Remove temporary workaround for function bitcastsJacob Gravelle2018-08-161-5/+0
| | | | | | | | | | | | | | Summary: EM_ASM no longer is lowered as varargs in C, so this workaround is obsolete. Reviewers: dschuff, sunfish Subscribers: sbc100, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D50859 llvm-svn: 339925
* [codeview] Use push_macro to avoid conflicts instead of a prefixReid Kleckner2018-08-161-170/+170
| | | | | | | | | | | | | | | | | | | | | | | Summary: This prefix was added in r333421, and it changed our dumper output to say things like "CVRegEAX" instead of just "EAX". That's a functional change that I'd rather avoid. I tested GCC, Clang, and MSVC, and all of them support #pragma push_macro. They don't issue warnings whem the macro is not defined either. I don't have a Mac so I can't test the real termios.h header, but I looked at the termios.h sources online and looked for other conflicts. I saw only the CR* macros, so those are the ones we work around. Reviewers: zturner, JDevlieghere Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D50851 llvm-svn: 339907
* AMDGPU: Custom lower fexpMatt Arsenault2018-08-163-1/+36
| | | | | | | | This will allow the library to just use __builtin_expf directly without expanding this itself. Note f64 still won't work because there is no exp instruction for it. llvm-svn: 339902
* [MC][X86] Enhance X86 Register expression handling to more closely match GCC.Nirav Dave2018-08-162-7/+14
| | | | | | | | | | | | | | | | Allow the comparison of x86 registers in the evaluation of assembler directives. This generalizes and simplifies the extension from r334022 to catch another case found in the Linux kernel. Reviewers: rnk, void Reviewed By: rnk Subscribers: hiraditya, nickdesaulniers, llvm-commits Differential Revision: https://reviews.llvm.org/D50795 llvm-svn: 339895
* Add support for AVX-512 CodeView registers.Zachary Turner2018-08-161-114/+170
| | | | | | | | | | | When compiling with /arch:AVX512 and optimizations turned on, we could crash while emitting debug info because we did not have CodeView register constants for the AVX 512 register set defined. This patch defines them. Differential Revision: https://reviews.llvm.org/D50819 llvm-svn: 339893
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