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* In the initial exec mode we always do a load to find the address of a variable.Rafael Espindola2012-06-291-4/+4
| | | | | | | | | Before this patch in pic 32 bit code we would add the global base register and not load from that address. This is a really old bug, but before the introduction of the tls attributes we would never select initial exec for pic code. llvm-svn: 159409
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-294-47/+62
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. llvm-svn: 159406
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-294-23/+60
| | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 llvm-svn: 159402
* Changed the formatting sequence of a curly brace to Jack Carter2012-06-281-2/+2
| | | | | | the comment per code review feedback. llvm-svn: 159376
* Remove layering violation #include.Bill Wendling2012-06-281-1/+0
| | | | llvm-svn: 159372
* The Mips specific inline asm operand modifier 'z' has theJack Carter2012-06-281-1/+13
| | | | | | | | following description in the gnu sources: Print $0 if operand is zero otherwise print the op normally. llvm-svn: 159324
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-287-16/+14
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* This allows hello world to be compiled for Mips 64 direct object.Jack Carter2012-06-271-0/+1
| | | | | | | | | | | It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack llvm-svn: 159302
* This allows hello world to be compiled for Mips 64 direct object.Jack Carter2012-06-274-3/+54
| | | | | | | | | | | It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack llvm-svn: 159301
* Whitespace.Chad Rosier2012-06-271-34/+34
| | | | llvm-svn: 159300
* The ELF relocation record format is different for N64 Jack Carter2012-06-271-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | which many Mips 64 ABIs use than for O64 which many if not all other target ABIs use. Most architectures have the following 64 bit relocation record format: typedef struct { Elf64_Addr r_offset; /* Address of reference */ Elf64_Xword r_info; /* Symbol index and type of relocation */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset; Elf64_Xword r_info; Elf64_Sxword r_addend; } Elf64_Rela; Whereas N64 has the following format: typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ Elf64_Sxword r_addend; } Elf64_Rela; The structure is the same size, but the r_info data element is now 5 separate elements. Besides the content aspects, endian byte reordering will be different for the area with each element being endianized separately. I treat this as generic and continue to pass r_type as an integer masking and unmasking the byte sized N64 values for N64 mode. I've implemented this and it causes no affect on other current targets. This passes make check. Jack llvm-svn: 159299
* Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton2012-06-271-1/+1
| | | | llvm-svn: 159259
* Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton2012-06-271-1/+2
| | | | | | instruction llvm-svn: 159257
* Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka2012-06-271-1/+1
| | | | llvm-svn: 159243
* Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2012-06-272-3/+10
| | | | llvm-svn: 159240
* Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng2012-06-261-0/+2
| | | | | | possible. Sorry. rdar://11745134 llvm-svn: 159236
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-267-4/+132
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-269-9/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* Removed unused variableElena Demikhovsky2012-06-261-1/+0
| | | | llvm-svn: 159197
* Rename to match other X86_64* names.Bill Wendling2012-06-263-5/+5
| | | | llvm-svn: 159196
* Shuffle optimization for AVX/AVX2.Elena Demikhovsky2012-06-261-0/+52
| | | | | | | | | | | | | | | | | | The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction. Before: vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3] vextractf128 $1, %ymm1, %xmm1 vextractf128 $1, %ymm0, %xmm0 vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3] vinsertf128 $1, %xmm0, %ymm2, %ymm0 After: vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4] vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4] vunpcklps %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] llvm-svn: 159188
* Remove some duplicate instructions that exist only to given different ↵Craig Topper2012-06-261-16/+13
| | | | | | mnemonics for the assembler. Use InstAlias instead. llvm-svn: 159184
* Make some ugly hacks for inline asm operands which name a specific register ↵Eli Friedman2012-06-251-2/+5
| | | | | | a bit more thorough. PR13196. llvm-svn: 159176
* ARM: update peephole optimization.Manman Ren2012-06-251-2/+18
| | | | | | | | | | More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 llvm-svn: 159166
* Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because ↵Craig Topper2012-06-251-0/+3
| | | | | | there are no patterns in the instruction. llvm-svn: 159127
* Remove codegen only instruction in favor of one that has the same ↵Craig Topper2012-06-252-13/+10
| | | | | | definition. Make some pattern operands more explicit about types. llvm-svn: 159126
* %RCX is not a function live-out in eh.return functions.Jakob Stoklund Olesen2012-06-241-2/+0
| | | | | | | | | | The function live-out registers must be live at all function returns, and %RCX is only used by eh.return. When a function also has a normal return, only %RAX holds a return value. This fixes PR13188. llvm-svn: 159116
* llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi2012-06-2411-0/+21
| | | | llvm-svn: 159112
* Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with ↵Craig Topper2012-06-242-24/+9
| | | | | | patterns. llvm-svn: 159109
* Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with ↵Craig Topper2012-06-242-22/+13
| | | | | | patterns. llvm-svn: 159108
* Fix build failures from r159106.Craig Topper2012-06-242-4/+2
| | | | llvm-svn: 159107
* Remove intrinsic specific instructions for CVTPD2PS and replace with just ↵Craig Topper2012-06-241-19/+13
| | | | | | patterns. llvm-svn: 159106
* Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns.Craig Topper2012-06-242-25/+12
| | | | llvm-svn: 159105
* Remove code i'd been testing with but didn't mean to commit. OopsPete Cooper2012-06-241-2/+0
| | | | llvm-svn: 159094
* DAG legalisation can now handle illegal fma vector types by scalarisationPete Cooper2012-06-241-0/+2
| | | | llvm-svn: 159092
* Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead ↵Craig Topper2012-06-232-34/+16
| | | | | | instead. llvm-svn: 159090
* Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional ↵Craig Topper2012-06-232-9/+11
| | | | | | change because there are no patterns in the instructions. Also fix a typo in a comment. llvm-svn: 159087
* Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to ↵Craig Topper2012-06-232-87/+84
| | | | | | the SSE2 section of the file. llvm-svn: 159086
* Add a microoptimization note.Benjamin Kramer2012-06-231-0/+6
| | | | llvm-svn: 159082
* Extend the IL for selecting TLS models (PR9788)Hans Wennborg2012-06-232-8/+57
| | | | | | | | | | | | | | | This allows the user/front-end to specify a model that is better than what LLVM would choose by default. For example, a variable might be declared as @x = thread_local(initialexec) global i32 42 if it will not be used in a shared library that is dlopen'ed. If the specified model isn't supported by the target, or if LLVM can make a better choice, a different model may be used. llvm-svn: 159077
* Use correct memory types for (V)CVTDQ2PD instructions.Craig Topper2012-06-231-3/+3
| | | | llvm-svn: 159075
* Silence an unused variable warning on release builds.Craig Topper2012-06-231-2/+2
| | | | llvm-svn: 159074
* Compress flags in X86 op folding to reduce space in static tables.Craig Topper2012-06-231-16/+16
| | | | llvm-svn: 159073
* Make helper method static since it doesn't use anything in the class.Craig Topper2012-06-231-3/+3
| | | | llvm-svn: 159071
* Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with ↵Craig Topper2012-06-232-26/+9
| | | | | | intrinsic patterns. Mem forms omitted because the load size is only 64-bits. llvm-svn: 159070
* Handle aliases to tls variables in all architectures, not just x86.Rafael Espindola2012-06-232-8/+11
| | | | llvm-svn: 159058
* (sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng2012-06-233-7/+21
| | | | | | | | | | | | | | | There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
* ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach2012-06-222-2/+13
| | | | | | | | | | | As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
* Add support for the PPC isel instruction.Hal Finkel2012-06-228-14/+84
| | | | | | | The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. llvm-svn: 159045
* Whitespace.Chad Rosier2012-06-221-8/+8
| | | | llvm-svn: 159035
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