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* Simplify a README.txt entry significantly to expose the core issue.Chandler Carruth2011-01-161-28/+26
| | | | llvm-svn: 123556
* 80-col.Eric Christopher2011-01-151-2/+4
| | | | llvm-svn: 123505
* Fix a comment.Bob Wilson2011-01-151-2/+2
| | | | llvm-svn: 123497
* Fix 80-cols.Eric Christopher2011-01-141-7/+14
| | | | llvm-svn: 123494
* 'HiReg' is written but never read. Nuke itsTed Kremenek2011-01-141-5/+5
| | | | | | | | declaration and its assignments. Found by clang static analyzer. llvm-svn: 123486
* Add a possibility to switch between CFI directives- and table-based frame ↵Anton Korobeynikov2011-01-142-5/+5
| | | | | | description emission. Currently all the backends use table-based stuff. llvm-svn: 123476
* CleanupAnton Korobeynikov2011-01-141-6/+1
| | | | llvm-svn: 123475
* revert my fastisel patch again which apparently still gives theChris Lattner2011-01-141-1/+1
| | | | | | llvm-gcc-i386-linux-selfhost buildbot heartburn... llvm-svn: 123431
* reapply r123414 now that the botz are calmed down and the fix is already in.Chris Lattner2011-01-141-1/+1
| | | | llvm-svn: 123427
* Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.Evan Cheng2011-01-143-28/+72
| | | | | | | | - Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first. - Added support for Thumb2 :lower16: and :upper16: fix up. - Added :upper16: and :lower16: relocation support to mach-o object writer. llvm-svn: 123424
* r123414 broke llvm-gcc bootstrap apparently, revertChris Lattner2011-01-141-1/+1
| | | | llvm-svn: 123422
* fix PR8961 - a fast isel miscompilation where we'd insert a new instructionChris Lattner2011-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | after sext's generated for addressing that got folded. Previously we compiled test5 into: _test5: ## @test5 ## BB#0: movq -8(%rsp), %rax ## 8-byte Reload movq (%rdi,%rax), %rdi addq %rdx, %rdi movslq %esi, %rax movq %rax, -8(%rsp) ## 8-byte Spill movq %rdi, %rax ret which is insane and wrong. Now we produce: _test5: ## @test5 ## BB#0: movslq %esi, %rax movq (%rdi,%rax), %rax addq %rdx, %rax ret llvm-svn: 123414
* Recognize alternative register names like ip -> r12.Owen Anderson2011-01-131-3/+14
| | | | | | Fixes <rdar://problem/8857982>. llvm-svn: 123409
* Fix a few more places that should use MBB::getLastNonDebugInstr().Jakob Stoklund Olesen2011-01-133-3/+3
| | | | llvm-svn: 123408
* typoChris Lattner2011-01-131-1/+1
| | | | llvm-svn: 123406
* memcpy + metadata = bliss :)Chris Lattner2011-01-131-0/+48
| | | | llvm-svn: 123405
* Add support to the ARM MC infrastructure to support mcr and friends. This ↵Owen Anderson2011-01-134-29/+225
| | | | | | | | | | | | | | requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
* Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen2011-01-1312-24/+26
| | | | llvm-svn: 123399
* Tidy comments, indentation, and 80-column violations.Bob Wilson2011-01-131-37/+39
| | | | llvm-svn: 123397
* Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target andKevin Enderby2011-01-131-2/+4
| | | | | | directional local labels like 1f and 2b. llvm-svn: 123393
* When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctlyJim Grosbach2011-01-131-4/+7
| | | | | | | | | set up the source operands. The original instr has an immediate operand that should be replaced with the frame reg operand rather than just adding the reg operand. Previously, the instruction ended up with too many operands causing an assert() when adding the default predicate. rdar://8825456 llvm-svn: 123387
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-139-75/+219
| | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
* Experiment with changing the default 32-bit linux stack alignment toEric Christopher2011-01-131-3/+3
| | | | | | 16 bytes for PR8969. Update all testcases accordingly. llvm-svn: 123367
* Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 orKevin Enderby2011-01-131-2/+12
| | | | | | | | .code 32 if the TargetMachine's isThumb() boolean does not match. The correct fix is to switch ARM subtargets at that point and is tracked by rdar://8856789 which is bigger task. llvm-svn: 123353
* Change call to Error() to assert()Jason W Kim2011-01-131-4/+1
| | | | llvm-svn: 123350
* Added clarifying commentJason W Kim2011-01-121-0/+2
| | | | llvm-svn: 123341
* JimG sez: "The value-kinds look like masks, but they're not consistently usedJason W Kim2011-01-121-2/+2
| | | | | | | | | | | that way, unfortunately. If you want to change them to work additively instead of a one-variant-kind-per-symbolref, that's great and I completely agree it's worth doing, but it really should be a separate patch. Until then, this isn't correct." So I am reverting this bit until a more opportune time. llvm-svn: 123340
* Sort the register list based on the *actual* register numbers rather than theBill Wendling2011-01-121-5/+5
| | | | | | enum values we give to them. <rdar://problem/8823730> llvm-svn: 123321
* Mostly undo r123297, but move the default case in EvaluateAsPCRel to the topMatt Beaumont-Gay2011-01-121-3/+3
| | | | | | of the switch block to appease GCC. llvm-svn: 123317
* Add another note taken from the gcc bugzilla.Nick Lewycky2011-01-121-1/+20
| | | | llvm-svn: 123315
* Implement RETURNADDR and FRAMEADDR lowering in SPARC backend.Venkatraman Govindaraju2011-01-123-4/+85
| | | | llvm-svn: 123310
* Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to Venkatraman Govindaraju2011-01-122-3/+5
| | | | | | ensure %o7 is not assigned as the destination of getpcx instruction. llvm-svn: 123304
* Fix SPARC backend call instruction so that arguments passed through registersVenkatraman Govindaraju2011-01-122-11/+24
| | | | | | | are correctly marked as used instead of passing all possible argument registers as used. llvm-svn: 123301
* Prefer llvm_unreachable to assert(0)Matt Beaumont-Gay2011-01-121-3/+3
| | | | llvm-svn: 123297
* 1. Support ELF pcrel relocations for movw/movt:Jason W Kim2011-01-124-5/+49
| | | | | | | | R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) llvm-svn: 123294
* Workaround for bug 8721.Jason W Kim2011-01-111-0/+106
| | | | | | .s Test added. llvm-svn: 123292
* SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CCVenkatraman Govindaraju2011-01-111-15/+19
| | | | llvm-svn: 123281
* Clean up ARM subtarget code by using Triple ADT.Evan Cheng2011-01-116-13/+15
| | | | llvm-svn: 123276
* McARM: Fill in GetMnemonicAcceptInfo().Daniel Dunbar2011-01-111-2/+17
| | | | llvm-svn: 123253
* Fix a comment: We now have intrinsics for vcvtr.Bob Wilson2011-01-111-1/+0
| | | | llvm-svn: 123246
* Fix PR8946, a missing reg/reg form of movdqu.Chris Lattner2011-01-111-0/+4
| | | | llvm-svn: 123242
* McARM: Sketch some logic for determining when to add carry set and ↵Daniel Dunbar2011-01-111-4/+48
| | | | | | predication code operands based on the "canonical mnemonic". llvm-svn: 123239
* McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out theDaniel Dunbar2011-01-111-11/+32
| | | | | | | | | | carry setting flag from the mnemonic. Note that this currently involves me disabling a number of working cases in arm_instructions.s, this is a hopefully short term evil which will be rapidly fixed (and greatly surpassed), assuming my current approach flies. llvm-svn: 123238
* Fix a thinko in 123226 that caused test failures on "other" platforms.Kalle Raiskila2011-01-111-1/+1
| | | | llvm-svn: 123229
* Add a "nop filler" pass to SPU.Kalle Raiskila2011-01-116-1/+166
| | | | | | | | | | | | | | | Filling no-ops is done just before emitting of assembly, when the instruction stream is final. No-ops are inserted to align the instructions so the dual-issue of the pipeline is utilized. This speeds up generated code with a minimum of 1% on a select set of algorithms. This pass may be redundant if the instruction scheduler and all subsequent passes that modify the instruction stream (prolog+epilog inserter, register scavenger, are there others?) are made aware of the instruction alignments. llvm-svn: 123226
* Teach constant folding to perform conversions from constant floatingChandler Carruth2011-01-111-55/+0
| | | | | | | | point values to their integer representation through the SSE intrinsic calls. This is the last part of a README.txt entry for which I have real world examples. llvm-svn: 123206
* Fix a random missed optimization by making InstCombine more aggressive when ↵Owen Anderson2011-01-111-15/+0
| | | | | | | | determining which bits are demanded by a comparison against a constant. llvm-svn: 123203
* Even if we don't have 7 bytes of stack space we may need to save andEric Christopher2011-01-111-1/+8
| | | | | | | | restore the stack pointer from the frame pointer on thumbv6. Fixes rdar://8819685 llvm-svn: 123196
* Expand on the safeness of restoring the sp from the fp a bit more.Eric Christopher2011-01-101-1/+2
| | | | llvm-svn: 123193
* +0.0 vs -0.0 differences can be handled by looking at the user of theChris Lattner2011-01-101-3/+19
| | | | | | operation in some cases. llvm-svn: 123190
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