summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* bugfix: When the source register of CALL_NOLINK was LR, the following code ↵Lauro Ramos Venancio2007-03-203-19/+28
| | | | | | | | | | was emitted: mov lr, pc bx lr So, the function was not called. llvm-svn: 35218
* Make two piece constant generation as a single instruction. It's ↵Evan Cheng2007-03-202-30/+55
| | | | | | re-materialized as a load from constantpool. llvm-svn: 35207
* New entry.Evan Cheng2007-03-201-0/+13
| | | | llvm-svn: 35206
* Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng2007-03-2012-16/+99
| | | | llvm-svn: 35205
* Two changes:Chris Lattner2007-03-202-13/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
* fix indentationChris Lattner2007-03-201-1/+1
| | | | llvm-svn: 35202
* fix obvious comment bugDale Johannesen2007-03-201-1/+1
| | | | llvm-svn: 35196
* Fix naming inconsistencies.Evan Cheng2007-03-196-30/+30
| | | | llvm-svn: 35163
* Special LDR instructions to load from non-pc-relative constantpools. These areEvan Cheng2007-03-193-2/+12
| | | | | | rematerializable. Only used for constant generation for now. llvm-svn: 35162
* Constant generation instructions are re-materializable.Evan Cheng2007-03-192-5/+11
| | | | llvm-svn: 35161
* Added isReMaterializable.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35160
* fix a warningChris Lattner2007-03-191-1/+1
| | | | llvm-svn: 35152
* minor updatesChris Lattner2007-03-181-8/+6
| | | | llvm-svn: 35143
* This is implemented. We now generate:Nick Lewycky2007-03-181-40/+0
| | | | | | | | | | | | | | | | | | | | | | entry: icmp ugt i32 %x, 4 ; <i1>:0 [#uses=1] br i1 %0, label %cond_true, label %cond_false cond_true: ; preds = %entry %tmp1 = tail call i32 (...)* @bar( i32 12 ) ; <i32> [#uses=0] ret void cond_false: ; preds = %entry switch i32 %x, label %cond_true15 [ i32 4, label %cond_true3 i32 3, label %cond_true7 i32 2, label %cond_true11 i32 0, label %cond_false17 ] ... llvm-svn: 35142
* Support 'I' inline asm constraint.Devang Patel2007-03-171-0/+11
| | | | llvm-svn: 35129
* Only ARMv6 has BSWAP.Lauro Ramos Venancio2007-03-161-0/+4
| | | | | | Fix MultiSource/Applications/aha test. llvm-svn: 35128
* And now support for MMX logical operations.Bill Wendling2007-03-162-2/+54
| | | | llvm-svn: 35125
* Added isLegalAddressExpression(). Only allows X +/- C for now.Evan Cheng2007-03-162-0/+21
| | | | llvm-svn: 35122
* Multiplication support for MMX.Bill Wendling2007-03-152-1/+9
| | | | llvm-svn: 35118
* Under X86-64 large code model, do not emit 32-bit pc relative calls.Evan Cheng2007-03-141-3/+5
| | | | llvm-svn: 35108
* Notes about codegen issues.Evan Cheng2007-03-141-0/+47
| | | | llvm-svn: 35107
* Clean up.Evan Cheng2007-03-141-3/+4
| | | | llvm-svn: 35105
* Oops.Evan Cheng2007-03-141-1/+1
| | | | llvm-svn: 35104
* X86-64 JIT is in large code model. Need stubs for direct calls.Evan Cheng2007-03-141-1/+1
| | | | llvm-svn: 35097
* x86-64 JIT stub codegen.Evan Cheng2007-03-141-0/+11
| | | | llvm-svn: 35096
* Preliminary support for X86-64 JIT stub codegen.Evan Cheng2007-03-141-3/+35
| | | | llvm-svn: 35095
* AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]Evan Cheng2007-03-131-0/+23
| | | | llvm-svn: 35088
* Zero is always a legal AM immediate.Evan Cheng2007-03-131-0/+3
| | | | llvm-svn: 35087
* Stack and register alignment of call arguments in the ELF ABINicolas Geoffray2007-03-131-6/+52
| | | | llvm-svn: 35083
* Implement getTargetLowering() or else LSR won't be using ARM specific hooks.Evan Cheng2007-03-132-1/+8
| | | | llvm-svn: 35077
* Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.Evan Cheng2007-03-122-8/+88
| | | | llvm-svn: 35075
* More flexible TargetLowering LSR hooks for testing whether an immediate is a ↵Evan Cheng2007-03-122-5/+10
| | | | | | legal target address immediate or scale. llvm-svn: 35074
* More flexible TargetLowering LSR hooks for testing whether an immediate isEvan Cheng2007-03-122-16/+33
| | | | | | a legal target address immediate or scale. llvm-svn: 35073
* Stupid bug: SSE2 supports v2i64 add / sub.Evan Cheng2007-03-121-0/+2
| | | | llvm-svn: 35070
* Adding more arithmetic operators to MMX. This is an almost exact copy ofBill Wendling2007-03-102-0/+14
| | | | | | the addition. Please let me know if you have suggestions. llvm-svn: 35055
* Minor stuff.Evan Cheng2007-03-091-0/+4
| | | | llvm-svn: 35049
* Add comments about LSR / ARM.Evan Cheng2007-03-091-0/+4
| | | | llvm-svn: 35048
* Unfinished work and ideas related to register scavenger.Evan Cheng2007-03-091-0/+14
| | | | llvm-svn: 35047
* apply comments from review of last patchDale Johannesen2007-03-091-2/+2
| | | | llvm-svn: 35045
* Add some observations from CoreGraphics benchmark. Remove registerDale Johannesen2007-03-091-47/+47
| | | | | | scavenging todo item, since it is now implemented. llvm-svn: 35044
* Implement inline asm modifier c.Evan Cheng2007-03-081-0/+3
| | | | llvm-svn: 35035
* Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so thatBill Wendling2007-03-084-10/+73
| | | | | | moves, loads, etc. are recognized. llvm-svn: 35031
* Fix a typo.Evan Cheng2007-03-081-1/+1
| | | | llvm-svn: 35030
* Putting more constants which do not contain relocations into .literal{4|8|16}Evan Cheng2007-03-083-16/+21
| | | | llvm-svn: 35026
* Change register allocation order to Dale's suggestion.Evan Cheng2007-03-081-14/+18
| | | | llvm-svn: 35021
* Bug fix. Not advancing the register scavenger iterator correctly.Evan Cheng2007-03-081-8/+21
| | | | llvm-svn: 35020
* For Darwin, put constant data into .const, .const_data, .literal{4|8|16}Evan Cheng2007-03-084-4/+53
| | | | | | sections. llvm-svn: 35017
* Put constant data to .const, .const_data, .literal{4|8|16} sections.Evan Cheng2007-03-082-2/+25
| | | | llvm-svn: 35016
* Add ReadOnlySection directive.Evan Cheng2007-03-081-0/+1
| | | | llvm-svn: 35015
* Only safe to use a call-clobbered or spilled callee-saved register as ↵Evan Cheng2007-03-071-2/+8
| | | | | | scratch register. llvm-svn: 35010
OpenPOWER on IntegriCloud