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* [MIPS][LLVM-MC] Fix Disassemble of Negative OffsetSagar Thakur2016-05-241-8/+8
| | | | | | | | | | | Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
* [CostModel][X86][XOP] Added XOP costmodel for BITREVERSE Simon Pilgrim2016-05-242-1/+49
| | | | | | Now that we have a nice fast VPPERM solution. Added framework for future intrinsic costs as well. llvm-svn: 270537
* [WebAssembly] Basic TargetTransformInfo support for SIMD128.Dan Gohman2016-05-232-1/+65
| | | | llvm-svn: 270508
* [SPARC] Fix 8 and 16-bit atomic load and store.James Y Knight2016-05-232-14/+22
| | | | | | | | | They were accidentally using the 32-bit load/store instruction for 8/16-bit operations, due to incorrect patterns (8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes) llvm-svn: 270486
* fix typo; NFCSanjay Patel2016-05-231-1/+1
| | | | llvm-svn: 270469
* use range-loop; NFCISanjay Patel2016-05-231-4/+2
| | | | llvm-svn: 270467
* [WebAssembly] Speed up LiveIntervals updating.Dan Gohman2016-05-231-6/+9
| | | | | | | | Use the more specific LiveInterval::removeSegment instead of LiveInterval::shrinkToUses when we know the specific range that's being removed. llvm-svn: 270463
* [Hexagon] Move some debug-only variable declarations into DEBUGKrzysztof Parzyszek2016-05-231-19/+21
| | | | llvm-svn: 270459
* Removing a switch statement that contains only a default label; NFC.Aaron Ballman2016-05-231-3/+1
| | | | llvm-svn: 270444
* [BPF] Remove exit-on-error flag in test (PR27766)Diana Picus2016-05-232-4/+10
| | | | | | | | | | | | | | The exit-on-error flag on the many_args1.ll test is needed to avoid an unreachable in BPFTargetLowering::LowerCall. We can also avoid it by ignoring any superfluous arguments to the call (i.e. any arguments after the first 5). Fixes PR27766. Differential Revision: http://reviews.llvm.org/D20471 v2 of r270419 llvm-svn: 270440
* Reverts "[BPF] Remove exit-on-error flag in test (PR27766)"Renato Golin2016-05-232-8/+4
| | | | | | | | This patch reverts r270419 because it broke a lot of buildbots, mostly Windows. We'd like help in investigating the issues, but for now, it should stay out. llvm-svn: 270433
* [BPF] Remove exit-on-error flag in test (PR27766)Diana Picus2016-05-232-4/+8
| | | | | | | | | | The exit-on-error flag on the many_args1.ll test is needed to avoid an unreachable in BPFTargetLowering::LowerCall. We can also avoid it by ignoring any superfluous arguments to the call (i.e. any arguments after the first 5). Fixes PR27766 llvm-svn: 270419
* [Sparc] LEON erratum fix - Delay Slot Filler modification.Chris Dewhurst2016-05-231-0/+9
| | | | | | This code should have been with the previous check-in (r270417) and prevents the DelaySlotFiller pass being utilized in functions where the erratum fix has been applied as this will break the run-time code. llvm-svn: 270418
* [Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction.Chris Dewhurst2016-05-2310-9/+152
| | | | | | | | | | Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix. The code will have no effect for other Sparc, but non-LEON processors. Differential Review: http://reviews.llvm.org/D20353 llvm-svn: 270417
* [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow ↵Sam Kolton2016-05-232-175/+245
| | | | | | | | | | | | modifiers for imms. Reviewers: nhaustov, tstellarAMD Subscribers: kzhuravl, arsenm Differential Revision: http://reviews.llvm.org/D20166 llvm-svn: 270415
* Test commitJacob Baungard Hansen2016-05-231-1/+0
| | | | llvm-svn: 270414
* [X86] Use instruction aliases to replace custom asm parser code for ↵Craig Topper2016-05-233-51/+53
| | | | | | optimizing moves to use 2 byte VEX prefix. llvm-svn: 270394
* [AVX512] Add patterns to implement stores of extracts of least signficant ↵Craig Topper2016-05-221-0/+123
| | | | | | | | subvectors using XMM or YMM stores instead of the vector extract instructions. Similar is already done for AVX and we had lost it going to AVX512VL. llvm-svn: 270383
* [x86, AVX] don't add a vzeroupper if that's what the code is already doing ↵Sanjay Patel2016-05-221-0/+6
| | | | | | | | | | | | | | | (PR27823) This isn't the complete fix, but it handles the trivial examples of duplicate vzero* ops in PR27823: https://llvm.org/bugs/show_bug.cgi?id=27823 ...and amusingly, the bogus cases already exist as regression tests, so let's take this baby step. We'll need to do more in the general case where there's legitimate AVX usage in the function + there's already a vzero in the code. Differential Revision: http://reviews.llvm.org/D20477 llvm-svn: 270378
* [AVX512] Implement missing patterns for any_extend load lowering.Igor Breger2016-05-222-55/+88
| | | | | | Differential Revision: http://reviews.llvm.org/D20513 llvm-svn: 270357
* [AVX512] The AVX512 file only need subtract_subvector index 0 patterns where ↵Craig Topper2016-05-221-15/+35
| | | | | | the source is 512-bits. The 256-bit source patterns were redundant with AVX. llvm-svn: 270356
* [AVX512] Add an AddedComplexity line to the 512-bit insert_subvector undef ↵Craig Topper2016-05-221-0/+2
| | | | | | index 0 patterns. This gives them higher priority than the memory patterns. This matches AVX1/2. llvm-svn: 270355
* [AVX512] Change the AddedComplexity on some patterns to match their AVX/SSE ↵Craig Topper2016-05-221-9/+13
| | | | | | equivalents. This helps group them close together in the isel tables and enable table compression. llvm-svn: 270354
* [AVX512] Add a couple patterns to fix some cases where two vector mask ↵Craig Topper2016-05-221-0/+11
| | | | | | inversions could appear in a row. llvm-svn: 270344
* [AVX512] Remove seemingly unnecessary AddedComplexity adjustment.Craig Topper2016-05-221-2/+0
| | | | llvm-svn: 270343
* [X86] Remove unnecessary alignment check on patterns that use VEXTRACTF128 ↵Craig Topper2016-05-211-8/+8
| | | | | | for integer types when only AVX1 is supported. llvm-svn: 270335
* [AVX512] Add patterns for extracting subvectors and storing to memory.Craig Topper2016-05-212-10/+15
| | | | llvm-svn: 270334
* [AVX512] Capitalize the Z in VEXTRACTPSzmr. Lowercase z has been primarily ↵Craig Topper2016-05-211-2/+2
| | | | | | used to indicating the zero masking behavior which is not the case here. NFC llvm-svn: 270333
* [AVX512] Rename vector extract instructions so 'mr' intead of 'rm' to ↵Craig Topper2016-05-211-2/+2
| | | | | | reflect the fact that memory is the destination. llvm-svn: 270332
* [AVX512] Fix copy/paste mistake a I made in a comment.Craig Topper2016-05-211-1/+1
| | | | llvm-svn: 270331
* [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.Michael Zuckerman2016-05-214-7/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D20438 llvm-svn: 270322
* [Clang][AVX512][intrinsics] Fix vscalef intrinsics.Michael Zuckerman2016-05-215-8/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D20324 llvm-svn: 270321
* [AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable ↵Craig Topper2016-05-212-1/+9
| | | | | | AVX2 versions of vector extract when AVX512VL is enabled. llvm-svn: 270318
* [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when ↵Craig Topper2016-05-212-30/+38
| | | | | | AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones. llvm-svn: 270317
* [AVX512] Disable AVX/AVX2 VBROADCASTSS/VBROADCASTSD patterns when AVX512VL ↵Craig Topper2016-05-211-4/+4
| | | | | | is enabled. llvm-svn: 270316
* AMDGPU: Define priorities for register classesMatt Arsenault2016-05-211-11/+31
| | | | | | | | | | Allocating larger register classes first should give better allocation results (and more importantly for myself, make the lit tests more stable with respect to scheduler changes). Patch by Matthias Braun llvm-svn: 270312
* [AVX512] Disable AVX/AVX2 patterns for VPSADBW and VPMULUDQ when the ↵Craig Topper2016-05-211-4/+4
| | | | | | AVX512VL/AVX512BWI equivalents are available. llvm-svn: 270311
* [X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering ↵Craig Topper2016-05-212-12/+24
| | | | | | instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers. llvm-svn: 270310
* AMDGPU: Cleanup lowering actionsMatt Arsenault2016-05-213-292/+248
| | | | | | | | These are kind of a mess and hard to follow, particularly for loads and stores. Fix various redundant, unnecessary and dead settings. llvm-svn: 270307
* AMDGPU: Fix high bits after division optimizationMatt Arsenault2016-05-211-17/+36
| | | | | | | This is essentially doing a 24-bit signed division with FP. We need to truncate to the N bit result. llvm-svn: 270305
* [AVR] Add AVRMCAsmInfoDylan McKay2016-05-213-0/+60
| | | | llvm-svn: 270302
* AMDGPU: Fix verifier error when spilling SGPRsMatt Arsenault2016-05-211-0/+13
| | | | | | | | | | | The current SGPR spilling test does not stress this because it is using s_buffer_load instructions to increase SGPR pressure and spill, but their output operands have the same SReg_32_XM0 constraint. This fixes an error when the SReg_32 output from most instructions is spilled. llvm-svn: 270301
* AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0Matt Arsenault2016-05-211-6/+5
| | | | llvm-svn: 270300
* [AVR] Fix header files in MCTargetDescDylan McKay2016-05-216-4/+39
| | | | | | | Everything now compiles successfully, but there are still undefined references. llvm-svn: 270298
* AMDGPU: Handle cbranch vccz/vccnzMatt Arsenault2016-05-212-1/+21
| | | | llvm-svn: 270297
* AMDGPU: Implement ReverseBranchConditionMatt Arsenault2016-05-212-0/+10
| | | | llvm-svn: 270296
* AMDGPU: Implement AnalyzeBranchMatt Arsenault2016-05-212-1/+130
| | | | | | Original patch by Tom Stellard llvm-svn: 270295
* [WebAssembly] Optimize away return instructions using fallthroughs.Dan Gohman2016-05-216-10/+111
| | | | | | | | | This saves a small amount of code size, and is a first small step toward passing values on the stack across block boundaries. Differential Review: http://reviews.llvm.org/D20450 llvm-svn: 270294
* [AVR] Fix signuature of AVRTargetMachine constructorDylan McKay2016-05-202-4/+7
| | | | llvm-svn: 270292
* SDAG: Implement Select instead of SelectImpl in PPCDAGToDAGISelJustin Bogner2016-05-201-151/+209
| | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 270283
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