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* Fix more inconsistent line endings. NFC.Dimitry Andric2017-12-182-8/+8
| | | | llvm-svn: 321016
* [MachineOutliner] Recommit r320229Jessica Paquette2017-12-181-60/+174
| | | | | | | LR was undefined entering outlined functions that contain calls. This made the machine verifier unhappy when expensive checks were enabled. This fixes that. llvm-svn: 321014
* [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
| | | | | | This has the same issue as the early pass disabled in r321010. llvm-svn: 321013
* [PPC] Disable reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
| | | | | | It creates invalid instructions. PR35688. llvm-svn: 321010
* Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC.Dimitry Andric2017-12-181-7/+7
| | | | llvm-svn: 321009
* [Hexagon] Higher versions of HVX imply presence of lower versionsKrzysztof Parzyszek2017-12-181-6/+6
| | | | | | | The code in Hexagon_MC::completeHVXFeatures wasn't setting all HVX- related features correctly. llvm-svn: 321008
* Fix inconsistent line endings in ARCDisassembler.cpp. NFC.Dimitry Andric2017-12-181-3/+3
| | | | llvm-svn: 321006
* i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004Krzysztof Parzyszek2017-12-181-1/+2
| | | | llvm-svn: 321005
* [Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek2017-12-184-0/+38
| | | | | | Implement any-extend as zero-extend. llvm-svn: 321004
* [Hexagon] Prefer to widen HVX vectors instead of promotingKrzysztof Parzyszek2017-12-182-0/+14
| | | | llvm-svn: 321002
* [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specifiedSander de Smalen2017-12-181-1/+4
| | | | | | | | | | | | | | Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, fhahn, olista01, echristo, efriedma Reviewed By: fhahn Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D40363 llvm-svn: 320992
* Reland "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-181-15/+22
| | | | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. This version has the correct commit message. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41183 llvm-svn: 320991
* [Memcpy Loop Lowering] Remove the fixed int8 lowering.Sean Fertile2017-12-181-17/+7
| | | | | | | | Switch over to the lowering that uses target supplied operand types. Differential Revision: https://reviews.llvm.org/D41201 llvm-svn: 320989
* [ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524Diana Picus2017-12-181-9/+5
| | | | | | | | | r319524 has made more G_MERGE_VALUES/G_UNMERGE_VALUES pairs legal than are supported by the rest of the pipeline. Restrict that to only the cases that we can currently handle: packing 32-bit values into 64-bit ones, when we have hardware FP. llvm-svn: 320980
* Revert "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-181-22/+15
| | | | | | This reverts commit r320974. The commit message lacked the Differential Revison: line. llvm-svn: 320975
* [mips] Fix the target specific instruction verifierSimon Dardis2017-12-181-15/+22
| | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. Reviewers: atanasyan https://reviews.llvm.org/D41183 llvm-svn: 320974
* [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)Sander de Smalen2017-12-182-0/+68
| | | | | | | | | | | | | | Summary: Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40361 llvm-svn: 320973
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-12-183-10/+178
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 320970
* AArch64: work around how Cyclone handles "movi.2d vD, #0".Tim Northover2017-12-184-2/+39
| | | | | | | | | | | For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare circumstances. Work around the issue conservatively by avoiding the instruction entirely. This patch changes CodeGen so that problematic instructions are never generated, and the AsmParser so that an equivalent instruction is used (with a warning). llvm-svn: 320965
* [X86] Fix mistake that I made when splitting up the setOperationAction calls ↵Craig Topper2017-12-181-2/+2
| | | | | | | | recently. The block I moved things that need BWI and 512-bit or VLX is incorrectly qualified with just hasBWI || hasVLX. Here I've qualified it with hasBWI && (hasAVX512 || hasVLX) where the hasAVX512 will be replaced with allowing 512-bit vectors in an upcoming patch. llvm-svn: 320957
* [X86] Make the code that creates fmaddsub from build_vector of extracts and ↵Craig Topper2017-12-171-6/+15
| | | | | | | | | | | | | | | | | | | inserts functional and add tests. Summary: We had no tests for this and we couldn't do the optimization because of a bad use count check. We need to know how many non-undef pieces of the build vector were filled in and ensure our use count is equal to that. But on the shuffle combine version we need the use count to be 2. The missing coverage was noticed during the review of D40335. Reviewers: RKSimon, zvi, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41133 llvm-svn: 320950
* Remove superfluous break after a return. NFCI.Simon Pilgrim2017-12-171-1/+0
| | | | llvm-svn: 320941
* [X86DomainReassignment] Store legal domains in a std::bitset instead of ↵Craig Topper2017-12-171-16/+18
| | | | | | using a SmallVector that really only ever has one element as a set. llvm-svn: 320940
* [X86] Use extract_vector_elt instead of X86ISD::VEXTRACT for isel of vXi1 ↵Craig Topper2017-12-174-14/+15
| | | | | | extractions. llvm-svn: 320937
* [X86] Canonicalize extract_vector_elt from vXi1 to always return MVT::i32.Craig Topper2017-12-172-6/+7
| | | | | | This allows us to remove some isel patterns that allowed MVT::i8 result type. llvm-svn: 320936
* [X86] Don't create X86ISD::VEXTRACT nodes directly. Use EXTRACT_VECTOR_ELT ↵Craig Topper2017-12-171-5/+6
| | | | | | | | and allow that to be legaized to VEXTRACT. I think we can remove the VEXTRACT node completely and use a canonicalized EXTRACT_VECTOR_ELT instead. This is a first step. llvm-svn: 320935
* Fix unused variable warning.Simon Pilgrim2017-12-161-3/+2
| | | | llvm-svn: 320934
* [X86][AVX] lowerVectorShuffleAsBroadcast - aggressively peek through BITCASTsSimon Pilgrim2017-12-161-2/+26
| | | | | | | | Assuming we can safely adjust the broadcast index for the new type to keep it suitably aligned, then peek through BITCASTs when looking for the broadcast source. Fixes PR32007 llvm-svn: 320933
* [X86][AVX] Use extract128BitVector helper. NFCI.Simon Pilgrim2017-12-161-4/+1
| | | | llvm-svn: 320932
* [X86][AVX] Fix failed broadcast foldSimon Pilgrim2017-12-161-3/+7
| | | | | | Strip excess BITCASTs from EXTRACT_SUBVECTOR input llvm-svn: 320930
* [X86] Don't pass a zero input to the passthru operand of ↵Craig Topper2017-12-161-9/+6
| | | | | | | | getVectorMaskingNode/getScalarMaskingNode when its going to emit an ISD::OR/ISD::AND. NFCI In those cases, the pass thru operand of the methods isn't used. The calls to the scalar version were passing a MVT::i1 zero, which is an illegal type at the stage this code runs. llvm-svn: 320928
* [X86] Have getVectorMaskingNode return an ISD::AND for X86ISD::VPSHUFBITQMB ↵Craig Topper2017-12-161-0/+1
| | | | | | instead of creating a select with one input being 0. llvm-svn: 320927
* [X86] When using vpopcntdq for ctpop of v8i16 vectors, only promote to v8i32.Craig Topper2017-12-161-8/+7
| | | | | | Previously we promoted to v8i64, but we don't need to go all the way to 512-bits. If we have VLX we can use the 256-bit instruction. And even if we don't have VLX we can widen v8i32 to v16i32 and drop the upper half. llvm-svn: 320926
* [X86] Combine some more scheduler model entries using regular expressions.Craig Topper2017-12-164-200/+100
| | | | | | We had a lot of separate 32 and 64 instructions that had the same scheduling data. This merges them into the same regular expression. This is pretty consistent with a lot of other instructions. llvm-svn: 320924
* [X86] Use instrs instead of instregex for gather/scatter instructions in the ↵Craig Topper2017-12-164-130/+116
| | | | | | | | scheduler models. Combine into single InstrRW entries. The reduces the number of scheduler groups in subtarget info. llvm-svn: 320923
* [X86] Remove unneeded code for handling the old kunpck intrinsics.Craig Topper2017-12-162-13/+1
| | | | llvm-svn: 320917
* [PowerPC, AsmParser] Enable the mnemonic spell correctorHal Finkel2017-12-161-2/+15
| | | | | | | | | | | r307148 added an assembly mnemonic spelling correction support and enabled it on ARM. This enables that support on PowerPC as well. Patch by Dmitry Venikov, thanks! Differential Revision: https://reviews.llvm.org/D40552 llvm-svn: 320911
* [X86] Add 128 and 256-bit VPOPCNTDQ instructions. Adjust some tablegen ↵Craig Topper2017-12-161-64/+33
| | | | | | | | classes LZCNT/POPCNT. I think when this instruction was first published it was only for a Knights CPU and thus VLX version was missing. llvm-svn: 320910
* [X86] Add back the assert from r320830 that was reverted in r320850Craig Topper2017-12-161-0/+2
| | | | | | Hopefully r320864 has fixed the offending case that failed the assert. llvm-svn: 320898
* Fix WebAssembly backend for some LLVM API changesDavid Blaikie2017-12-156-11/+10
| | | | llvm-svn: 320893
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-15165-582/+574
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [Hexagon] Remove recursion in visitUsesOf, replace with use queueKrzysztof Parzyszek2017-12-152-43/+121
| | | | | | | | | | | | | | | | This is primarily to reduce stack usage, but ordering the use queue according to the position in the code (earlier instructions visited before later ones) reduces the number of unnecessary bottoms due to visiting instructions out of order, e.g. %reg1 = copy %reg0 %reg2 = copy %reg0 %reg3 = and %reg1, %reg2 Here, reg3 should be known to be same as reg0-2, but if reg3 is evaluated after reg1 is updated, but before reg2 is updated, the two inputs to the and will appear different, causing reg3 to become bottom. llvm-svn: 320866
* [Hexagon] Handle concat_vectors of all allowed HVX typesKrzysztof Parzyszek2017-12-151-10/+17
| | | | llvm-svn: 320865
* [X86] Use AND32ri8 instead of AND64ri8 in Asan code in EmitCallAsanReport ↵Craig Topper2017-12-151-1/+1
| | | | | | | | for 32-bit mode. This seemed to work due to a quirk in the X86 MC encoder that didn't emit a REX byte that the AND64ri8 implies when in 32-bit mode. This made the encoding the same as AND32ri8. I tried to add an assert to catch the dropped REX prefix that caught this. llvm-svn: 320864
* [X86] In LowerVectorCTPOP use ISD::ZERO_EXTEND/ISD::TRUNCATE instead of the ↵Craig Topper2017-12-151-4/+4
| | | | | | | | target specific nodes. The target independent nodes will get legalized to the target specific nodes by their own legalization process. Someday I'd like to stop using a target specific for zero extends and truncates of legal types so the less places we reference the target specific opcode the better. llvm-svn: 320863
* [X86] Remove unnecessary TODO.Craig Topper2017-12-151-1/+0
| | | | | | When I wrote it I thought we were missing a potential optimization for KNL. But investigating further shows that for KNL we still do the optimal thing by widening to v4f32 and then using special isel patterns to widen again to zmm a register. llvm-svn: 320862
* [Hexagon] Fix operand-swapping PatFrag for atomic storesKrzysztof Parzyszek2017-12-151-18/+22
| | | | | | | PatFrag now has the atomicity information stored as bit fields. They need to be copied to the new PatFrag. llvm-svn: 320855
* [X86] Remove assert in X86MCCodeEmitter.cpp that was added in r320830.Craig Topper2017-12-151-2/+0
| | | | | | It seems to be failing real code which is concerning, but we were silently getting away with it. I'll investigate further. llvm-svn: 320850
* [SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with ↵Craig Topper2017-12-151-3/+5
| | | | | | | | | | | | | | | | | | | | | | | non-constant index Summary: Currently we don't handle v32i1/v64i1 insert_vector_elt correctly as we fail to look at the number of elements closely and assume it can only be v16i1 or v8i1. We also can't type legalize v64i1 insert_vector_elt correctly on KNL due to the type not being byte addressable as required by the legalizing through memory accesses path requires. For the first issue, the patch now tries to pick a 512-bit register with the correct number of elements and promotes to that. For the second issue, we now extend the vector to a byte addressable type, do the stores to memory, load the two halves, and then truncate the halves back to the original type. Technically since we changed the type, we may not need two loads, but actually checking that is more work and for the v64i1 case we do need them. Reviewers: RKSimon, delena, spatel, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40942 llvm-svn: 320849
* [X86] Add 'Requires<[In64BitMode]>' to a bunch of instructions that only ↵Craig Topper2017-12-154-67/+94
| | | | | | | | have memory and immediate operands. The asm parser wasn't preventing these from being accepted in 32-bit mode. Instructions that use a GR64 register are protected by the parser rejecting the register in 32-bit mode. llvm-svn: 320846
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