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* ARM NEON: Don't need COPY_TO_REGCLASS in patternArnold Schwaighofer2013-02-191-3/+1
| | | | | | | | | | | | | | | | | In my previous commit: "Merge a f32 bitcast of a v2i32 extractelt A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers." I added a pattern containing a copy_to_regclass. The copy_to_regclass is actually not needed. radar://13191881 llvm-svn: 175555
* ARM: Allocation hints must make sure to be in the alloc order.Jim Grosbach2013-02-191-1/+2
| | | | | | | | | When creating an allocation hint for a register pair, make sure the hint for the physical register reference is still in the allocation order. rdar://13240556 llvm-svn: 175541
* Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h withJyotsna Verma2013-02-191-28/+60
| | | | | | HexagonInstrFormats.td. llvm-svn: 175537
* Clean up HiPE prologue emission a bit and avoid signed arithmetic tricks.Benjamin Kramer2013-02-191-43/+47
| | | | | | No intended functionality change. llvm-svn: 175536
* Move LLVM_LIBRARY_VISIBILITY for consistency with what was done toRafael Espindola2013-02-191-1/+1
| | | | | | PPCJITInfo.cpp in r175394. llvm-svn: 175531
* Make ARMAsmPrinter pass name more precise and fix comment.Eli Bendersky2013-02-191-6/+2
| | | | llvm-svn: 175527
* Make pass name more precise and fix comment.Eli Bendersky2013-02-191-6/+2
| | | | llvm-svn: 175525
* ARM NEON: Merge a f32 bitcast of a v2i32 extracteltArnold Schwaighofer2013-02-191-0/+6
| | | | | | | | | | | | | | A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 llvm-svn: 175520
* R600: Add AR_X to the R600_TReg_X register class.Tom Stellard2013-02-191-1/+1
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175519
* R600: Mark all members of the TRegMem register class as reservedTom Stellard2013-02-191-0/+6
| | | | | | | | This stops the Machine Verifier from complaining about uses of undefined physical registers. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175518
* R600: Fix scheduler crash caused by invalid MachinePointerInfoTom Stellard2013-02-191-1/+1
| | | | | | | | | | | | | | Kernel function arguments are lowered to loads from the PARAM_I address space. When creating these load instructions, we were initializing their MachinePointerInfo with an Arguement object that was not attached to any function. This was causing the MachineScheduler to crash when it tried to access the parent of the Arguement. This has been fixed by initializing the MachinePointerInfo with a UndefValue instead. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175517
* R600: Fix tracking of implicit defs in the IndirectAddressing passTom Stellard2013-02-191-7/+25
| | | | | | | | | In some cases, we were losing track of live implicit registers which was creating dead defs and causing the scheduler to produce invalid code. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175516
* Fix capitalization in comment to match function name.Craig Topper2013-02-191-1/+1
| | | | llvm-svn: 175497
* Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler2013-02-192-1/+48
| | | | | | BtnezT8SltiX16, BtnezT8SltiuX16 . llvm-svn: 175486
* Remove some unused private fields from the AArch64MCCodeEmitter. TheseChandler Carruth2013-02-191-7/+2
| | | | | | | | | | fields were only ever set in the constructor. The create method retains its consistent interface so that these bits can be re-threaded through the emitter if they're ever needed. This was found by the -Wunused-private-field Clang warning. llvm-svn: 175482
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-193-0/+58
| | | | llvm-svn: 175474
* Use array_pod_sort instead of std::sort.Jakub Staszak2013-02-181-2/+2
| | | | llvm-svn: 175472
* X86FrameLowering.cpp: Fixup. Sorry for the breakage.NAKAMURA Takumi2013-02-181-1/+1
| | | | llvm-svn: 175467
* Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.David Blaikie2013-02-183-6/+6
| | | | | | | Also removes some redundant DNI comments on function declarations already using the macro. llvm-svn: 175466
* X86FrameLowering.cpp: Fix a warning in -Asserts. [-Wunused-variable]NAKAMURA Takumi2013-02-181-2/+1
| | | | llvm-svn: 175464
* Remove a useless assert.Chad Rosier2013-02-181-1/+0
| | | | llvm-svn: 175463
* [fast-isel] Remove an invalid assert.Chad Rosier2013-02-181-1/+0
| | | | | | | | If the memcpy has an odd length with an alignment of 2, this would incorrectly assert on the last 1 byte copy. rdar://13202135 llvm-svn: 175459
* Fix a 32/64 bit incompatibility in the HiPE prologue generation.Benjamin Kramer2013-02-181-1/+1
| | | | llvm-svn: 175458
* Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.Benjamin Kramer2013-02-182-5/+157
| | | | llvm-svn: 175457
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-187-23/+15
| | | | llvm-svn: 175446
* R600: Support for TBOVincent Lejeune2013-02-183-1/+58
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175445
* R600: Increase number of ArrayBase Reg to 32Vincent Lejeune2013-02-181-2/+2
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175443
* Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler2013-02-181-0/+8
| | | | llvm-svn: 175420
* Expand pseudo/macro BteqzT8SltuX16 . There is no test case becauseReed Kotler2013-02-182-0/+7
| | | | | | | | at this time, llvm is generating a different but equivalent pattern that would lead to this instruction. I am trying to think of a way to get it to generate this. If I can't, I may just remove the pseudo. llvm-svn: 175419
* Expand pseudo/macro BteqzT8SltX16.Reed Kotler2013-02-181-0/+3
| | | | llvm-svn: 175417
* Expand macro/pseudo BteqzT8CmpX16.Reed Kotler2013-02-181-0/+3
| | | | llvm-svn: 175416
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-183-3/+34
| | | | | | | | | | This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. llvm-svn: 175413
* X86: Add a note.Benjamin Kramer2013-02-171-0/+9
| | | | llvm-svn: 175408
* [XCore] Add missing 2r instructions.Richard Osborne2013-02-173-1/+35
| | | | | | | These instructions are not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175407
* [XCore] Add TSETR instruction.Richard Osborne2013-02-173-1/+34
| | | | | | | This instruction is not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175406
* [XCore] Add missing u10 / lu10 instructions.Richard Osborne2013-02-171-1/+12
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175404
* [XCore] Add missing u6 / lu6 instructions.Richard Osborne2013-02-171-2/+18
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175403
* Return false instead of 0.Jakub Staszak2013-02-171-1/+1
| | | | llvm-svn: 175402
* AArch64: Avoid shifts by 64, that's undefined behavior.Benjamin Kramer2013-02-171-3/+3
| | | | | | No functionality change. llvm-svn: 175400
* Make the visibility of LLVMPPCCompilationCallback work with GCC.Benjamin Kramer2013-02-171-1/+1
| | | | | | | | | | | | GCC warns about the attribute being ignored if it occurs after void*. There seems to be some kind of incompatibility between clang and gcc here, but I can't fathom who's right. void* LLVM_LIBRARY_VISIBILITY foo(); // clang: hidden, gcc: default LLVM_LIBRARY_VISIBILITY void *bar(); // clang: hidden, gcc: hidden void LLVM_LIBRARY_VISIBILITY qux(); // clang: hidden, gcc: hidden llvm-svn: 175394
* Clean up mips16 td file in preparation for massive pseudo lowering work.Reed Kotler2013-02-161-71/+68
| | | | llvm-svn: 175379
* TypoRenato Golin2013-02-161-1/+1
| | | | llvm-svn: 175371
* One more try to make this look nice. I have lots of pseudo lowering Reed Kotler2013-02-162-4/+12
| | | | | | | | as well as 16/32 bit variants to do and so I want this to look nice when I do it. I've been experimenting with this. No new test cases are needed. llvm-svn: 175369
* [msvc x64] Update X86CompilationCallback_Win64.asm corresponding to r175267.NAKAMURA Takumi2013-02-161-2/+2
| | | | llvm-svn: 175363
* Target/R600/CMakeLists.txt: Prune SILowerLiteralConstants.cpp corresponding ↵NAKAMURA Takumi2013-02-161-1/+0
| | | | | | to r175354. llvm-svn: 175361
* Minor cleanups. No functionality change.Jakub Staszak2013-02-161-9/+8
| | | | llvm-svn: 175359
* R600/SI: Add pattern to simplify i64 loadingChristian Konig2013-02-162-0/+9
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175356
* R600/SI: nuke SReg_1 v3Christian Konig2013-02-167-118/+23
| | | | | | | | | | | | | | | | | It's completely unnecessary and can be replace with proper SReg_64 handling instead. This actually fixes a piglit test on SI. v2: use correct register class in addRegisterClass, set special classes as not allocatable v3: revert setting special classes as not allocateable This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175355
* R600/SI: cleanup literal handling v3Christian Konig2013-02-1610-195/+176
| | | | | | | | | | | | | | | | Seems to be allot simpler, and also paves the way for further improvements. v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW, use VGPR0 in dummy EXP, avoid compiler warning, break after encoding the first literal. v3: correctly use V_ADD_F32_e64 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175354
* R600/SI: replace AllReg_* with [SV]Src_* v2Christian Konig2013-02-163-85/+89
| | | | | | | | | | | | Mark all the operands that can also have an immediate. v2: SOFFSET is also an SSrc_32 operand This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175353
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