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* Instead of aborting if not a case we can handle specially, break out andChris Lattner2005-10-212-55/+52
| | | | | | | | let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc. also, reindent this code llvm-svn: 23874
* Plugin new subtarget backend into the build.Jim Laskey2005-10-215-80/+42
| | | | llvm-svn: 23870
* silence a release mode warningChris Lattner2005-10-211-1/+1
| | | | llvm-svn: 23868
* Match rotate. This does actually match the rotates in an rc5 cipher, but INate Begeman2005-10-211-0/+3
| | | | | | haven't seen it fire on our testsuite. llvm-svn: 23863
* Don't generate operations that aren't yet supportedNate Begeman2005-10-211-1/+4
| | | | llvm-svn: 23858
* Kill some now-dead code.Nate Begeman2005-10-211-159/+0
| | | | llvm-svn: 23857
* byte zap not immediate goodnessAndrew Lenharth2005-10-211-12/+47
| | | | llvm-svn: 23855
* Invert the TargetLowering flag that controls divide by consant expansion.Nate Begeman2005-10-214-56/+8
| | | | | | | | | | Add a new flag to TargetLowering indicating if the target has really cheap signed division by powers of two, make ppc use it. This will probably go away in the future. Implement some more ISD::SDIV folds in the dag combiner Remove now dead code in the x86 backend. llvm-svn: 23853
* Inst cleanup. As a bonus, operands are in the correct order for cmovs. ↵Andrew Lenharth2005-10-202-47/+33
| | | | | | Expect new stuff to pass in the JIT tonight llvm-svn: 23852
* Use a literal to define ineg instead of immzeroChris Lattner2005-10-201-2/+1
| | | | llvm-svn: 23851
* added a few 1 operand form stuff. Seems to break regalloc on alpha. sighAndrew Lenharth2005-10-203-13/+33
| | | | llvm-svn: 23849
* add cttz and ctpopAndrew Lenharth2005-10-201-0/+2
| | | | llvm-svn: 23848
* Sounds good, finish the intop conversion.Andrew Lenharth2005-10-201-27/+20
| | | | llvm-svn: 23843
* Add some more patterns for i64 on ppcNate Begeman2005-10-201-6/+12
| | | | llvm-svn: 23842
* Add some pattern fragments to simplify the repetitive parts of the patternsChris Lattner2005-10-201-3/+22
| | | | | | | | for some common ops and use them for a few examples. Andrew, if you like this, feel free to convert the rest over, if you hate it, feel free to revert. llvm-svn: 23837
* simplify this a bit by using immediatesChris Lattner2005-10-201-24/+16
| | | | llvm-svn: 23836
* Move the target constant divide optimization up into the dag combiner, soNate Begeman2005-10-203-314/+2
| | | | | | | that the nodes can be folded with other nodes, and we can not duplicate code in every backend. Alpha will probably want this too. llvm-svn: 23835
* forgot this oneAndrew Lenharth2005-10-201-0/+265
| | | | llvm-svn: 23833
* ret 0; works, not much elseAndrew Lenharth2005-10-207-139/+226
| | | | | | | | still lots of uglyness. Maybe calls will come soon. Fixing the return value of things will be necessary to make alpha work. llvm-svn: 23832
* This fixes PR638:John Criswell2005-10-191-6/+6
| | | | | | Regression/CodeGen/Generic/2004-02-08-UnwindSupport.llx llvm-svn: 23831
* Added InstrSchedClass to each of the PowerPC Instructions.Jim Laskey2005-10-199-389/+427
| | | | | | | Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
* Write patterns for the various shl and srl patterns that don't involveNate Begeman2005-10-193-50/+71
| | | | | | doing something clever. llvm-svn: 23824
* Push processor descriptions to the top of target and add command line info.Jim Laskey2005-10-197-23/+80
| | | | llvm-svn: 23820
* now that tblgen is smarter, use integers directly. This should help Andrew tooChris Lattner2005-10-191-4/+1
| | | | llvm-svn: 23818
* teach ppc backend these are copiesChris Lattner2005-10-191-1/+2
| | | | llvm-svn: 23813
* Convert these cases to patternsChris Lattner2005-10-192-37/+11
| | | | llvm-svn: 23811
* Woo, it kinda works. We now generate this atrociously bad, but correct,Nate Begeman2005-10-192-23/+54
| | | | | | | | | | | | | | | | | | | | | | | code for long long foo(long long a, long long b) { return a + b; } _foo: or r2, r3, r3 or r3, r4, r4 or r4, r5, r5 or r5, r6, r6 rldicr r2, r2, 32, 31 rldicl r3, r3, 0, 32 rldicr r4, r4, 32, 31 rldicl r5, r5, 0, 32 or r2, r3, r2 or r3, r5, r4 add r4, r3, r2 rldicl r2, r4, 32, 32 or r4, r4, r4 or r3, r2, r2 blr llvm-svn: 23809
* apply some tblgen majik to simplify the X register definitionsChris Lattner2005-10-191-19/+19
| | | | llvm-svn: 23805
* Make a new reg class for 64 bit regs that aliases the 32 bit regs. ThisNate Begeman2005-10-193-9/+50
| | | | | | | | | | | will have to tide us over until we get real subreg support, but it prevents the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor. Add some initial support for TRUNCATE and ANY_EXTEND, but they don't currently work due to issues with ScheduleDAG. Something wll have to be figured out. llvm-svn: 23803
* Add the ability to lower return instructions to TargetLowering. ThisNate Begeman2005-10-183-5/+32
| | | | | | | allows us to lower legal return types to something else, to meet ABI requirements (such as that i64 be returned in two i32 regs on Darwin/ppc). llvm-svn: 23802
* Simple edits; remove unimplimented cases and clarify long haul SLU cases.Jim Laskey2005-10-184-61/+3
| | | | llvm-svn: 23788
* Fix the JIT encoding of LWA, LD, STD, and STDU.Chris Lattner2005-10-183-4/+20
| | | | llvm-svn: 23787
* Checking in first round of scheduling tablegen files. Not tied in as yet.Jim Laskey2005-10-186-0/+947
| | | | llvm-svn: 23786
* add a caseChris Lattner2005-10-181-0/+3
| | | | llvm-svn: 23785
* Do the right thing and enable 64 bit regs under the control of a subtargetNate Begeman2005-10-183-8/+10
| | | | | | | option. Currently the only way to enable this is to specify the 64bitregs mattr flag. It is never enabled by default on any config yet. llvm-svn: 23779
* First bits of 64 bit PowerPC stuff, currently disabled. A lot of this isNate Begeman2005-10-189-88/+154
| | | | | | purely mechanical. llvm-svn: 23778
* More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman2005-10-1620-170/+152
| | | | | | redundant after the change. llvm-svn: 23759
* Remove some dead code now that the dag combiner exists.Nate Begeman2005-10-151-15/+0
| | | | llvm-svn: 23754
* Remove some dead code: the ORI/ORIS cases are autogen'd. This makesChris Lattner2005-10-151-42/+1
| | | | | | SelectIntImmediateExpr dead. llvm-svn: 23753
* prune #includesChris Lattner2005-10-152-3/+2
| | | | llvm-svn: 23752
* These instructions are now autogeneratedChris Lattner2005-10-151-34/+0
| | | | llvm-svn: 23751
* Add a pattern for FSQRTSChris Lattner2005-10-151-1/+1
| | | | llvm-svn: 23750
* remove dead codeChris Lattner2005-10-151-8/+3
| | | | llvm-svn: 23749
* remove broken SRA/rlwimi caseChris Lattner2005-10-151-11/+2
| | | | llvm-svn: 23746
* Rename PPC32*.h to PPC*.hChris Lattner2005-10-1414-17/+16
| | | | | | This completes the grand PPC file renaming llvm-svn: 23745
* Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfoChris Lattner2005-10-145-45/+22
| | | | | | and PPC32JITInfo classes should be merged. llvm-svn: 23744
* Rename PowerPC*.h to PPC*.hChris Lattner2005-10-1417-19/+19
| | | | llvm-svn: 23743
* Rename PowerPCInstrBuilder.h -> PPC*Chris Lattner2005-10-144-3/+3
| | | | llvm-svn: 23742
* Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachineChris Lattner2005-10-144-49/+24
| | | | | | still should be merged into the PPC32TargetMachine class llvm-svn: 23741
* Rename PowerPC*.td -> PPC*.tdChris Lattner2005-10-144-4/+4
| | | | llvm-svn: 23740
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