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* Remove debug prints from r238487Reid Kleckner2015-05-281-6/+1
| | | | llvm-svn: 238501
* Disable x86 tail call optimizations that jump through GOTReid Kleckner2015-05-281-2/+20
| | | | | | | | | | | | | | | | | | | | For x86 targets, do not do sibling call optimization when materializing the callee's address would require a GOT relocation. We can still do tail calls to internal functions, hidden functions, and protected functions, because they do not require this kind of relocation. It is still possible to get GOT relocations when the user explicitly asks for it with musttail or -tailcallopt, both of which are supposed to guarantee TCO. Based on a patch by Chih-hung Hsieh. Reviewers: srhines, timmurray, danalbert, enh, void, nadav, rnk Subscribers: joerg, davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D9799 llvm-svn: 238487
* Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM.Peter Collingbourne2015-05-286-33/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were previously codegen'ing these as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achiveing better codegen is to create LDM/STM instructions with identical sets of virtual registers, let the register allocator pick arbitrary registers and order register lists when printing an MCInst. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. This is implemented by lowering the memcpy intrinsic to a series of SD-only MCOPY pseudo-instructions which performs a memory copy using a given number of registers. During SD->MI lowering, we lower MCOPY to LDM/STM. This is a little unusual, but it avoids the need to encode register lists in the SD, and we can take advantage of SD use lists to decide whether to use the _UPD variant of the instructions. Fixes PR9199. Differential Revision: http://reviews.llvm.org/D9508 llvm-svn: 238473
* [WinEH] Remove debugging dump() callReid Kleckner2015-05-281-1/+0
| | | | llvm-svn: 238472
* Reuse Loc variable. NFC.Chad Rosier2015-05-281-1/+1
| | | | llvm-svn: 238448
* [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.Kai Nacke2015-05-283-2/+34
| | | | | | | | | | | | | Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
* [Mips64] Add support for MCJIT for MIPS64r2 and MIPS64r6Petar Jovanovic2015-05-281-2/+2
| | | | | | | | | | Add support for resolving MIPS64r2 and MIPS64r6 relocations in MCJIT. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D9667 llvm-svn: 238424
* Don't call utostr in Twine/raw_ostream contexts.Benjamin Kramer2015-05-282-13/+8
| | | | | | Creating temporary std::strings there is unnecessary. llvm-svn: 238412
* [NaryReassociate] Run EarlyCSE after NaryReassociateJingyue Wu2015-05-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch made two improvements to NaryReassociate and the NVPTX pipeline 1. Run EarlyCSE/GVN after NaryReassociate to get rid of redundant common expressions. 2. When adding an instruction to SeenExprs, maps both the SCEV before and after reassociation to that instruction. Test Plan: updated @reassociate_gep_nsw in nary-gep.ll Reviewers: meheff, broune Reviewed By: broune Subscribers: dberlin, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D9947 llvm-svn: 238396
* ARMTargetParser: Normalising build attributesRenato Golin2015-05-271-3/+3
| | | | | | | | | | | | | | | Now that most of the methods in Clang and LLVM that were parsing arch/cpu/fpu strings are using ARMTargetParser, it's time to make it a bit more conforming with what the ABI says. This commit adds some clarification on what build attributes are accepted and which are "non-standard". It also makes clear that the "defaultCPU" and "defaultArch" methods were really just build attribute getters. It also diverges from GCC's behaviour to say that armv2/armv3 are really an ARMv4 in the build attributes, when the ABI has a clear state for that: Pre-v4. llvm-svn: 238344
* R600: Rely on TypeLegalizer to use divrem instead of div/remJan Vesely2015-05-271-43/+0
| | | | | reviewer: tstellardAMD llvm-svn: 238337
* [mips][microMIPSr6] Implement SEB and SEH instructionsZoran Jovanovic2015-05-273-2/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D9739 llvm-svn: 238333
* [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC ↵Jozef Kolek2015-05-273-7/+89
| | | | | | | | | | | and BNEZALC instructions This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions using mapping. Differential Revision: http://reviews.llvm.org/D10031 llvm-svn: 238325
* AVX-512: Fixed a bug in extracting subvector from v64i1Elena Demikhovsky2015-05-271-0/+8
| | | | | | By Igor Breger (igor.breger@intel.com) llvm-svn: 238322
* Use operator<< instead of print in a few more places.Rafael Espindola2015-05-274-7/+7
| | | | llvm-svn: 238315
* Revert r238190 and r238197: [mips] Make TTypeEncoding indirect to allow ↵Daniel Sanders2015-05-272-9/+1
| | | | | | | | | | .eh_frame to be read-only. This broke the llvm-mips-linux builder and several of our out-of-tree builders. Initial investigations show that the commit probably isn't the problem but reverting anyway while I investigate. llvm-svn: 238302
* AVX-512: Implemented all forms of sign-extend and zero-extend instructions ↵Elena Demikhovsky2015-05-273-75/+160
| | | | | | | | | | | for KNL and SKX Implemented DAG lowering for all these forms. Added tests for DAG lowering and encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238301
* [X86] Implement the support for shrink-wrapping.Quentin Colombet2015-05-273-35/+68
| | | | | | | | | | | | | With this patch the x86 backend is now shrink-wrapping capable and this functionality can be tested by using the -enable-shrink-wrap switch. The next step is to make more test and enable shrink-wrapping by default for x86. Related to <rdar://problem/20821487> llvm-svn: 238293
* ARMLoadStoreOptimizer: Code cleanup; NFCMatthias Braun2015-05-271-15/+12
| | | | llvm-svn: 238289
* Print "lock \t foo" instead of "lock \n foo".Rafael Espindola2015-05-261-1/+1
| | | | | | | | | | | This gets gas and llc -filetype=obj to agree on the order of prefixes. For llvm-mc we need to fix the asm parser to know that it makes a difference on which line the "lock" is in. Part of pr23594. llvm-svn: 238232
* R600: Use SIGN_EXTEND_INREG for SEXT loadsJan Vesely2015-05-261-6/+3
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 238229
* R600: Add comments to subword private address load lowering codeJan Vesely2015-05-261-0/+13
| | | | | | | | v2: Use C++ comments and end with periods Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 238228
* Revert "Re-commit changes in r237579 with fix for bug breaking windows builds."Diego Novillo2015-05-266-628/+17
| | | | | | | This reverts commit r238201 to fix linking problems in x86 Linux http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150525/278413.html llvm-svn: 238223
* R600/SI: Add assembler support for all CI and VI VOP2 instructionsTom Stellard2015-05-263-3/+70
| | | | llvm-svn: 238211
* Replace getOrCreateSectionData with registerSection.Rafael Espindola2015-05-262-7/+7
| | | | | | There is now no SectionData to be created. llvm-svn: 238208
* Re-commit changes in r237579 with fix for bug breaking windows builds.Luke Cheeseman2015-05-266-17/+628
| | | | llvm-svn: 238201
* Test CommitLuke Cheeseman2015-05-261-1/+0
| | | | llvm-svn: 238199
* AVX-512: fixed a bug in arithmetic operations lowering for i1 typeElena Demikhovsky2015-05-261-0/+12
| | | | | | https://llvm.org/bugs/show_bug.cgi?id=23630 llvm-svn: 238198
* AVX-512: fixed a bug in lowering VSELECT for 512-bit vectorElena Demikhovsky2015-05-261-1/+1
| | | | | | https://llvm.org/bugs/show_bug.cgi?id=23634 llvm-svn: 238195
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-2627-949/+974
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.Daniel Sanders2015-05-262-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Following on from r209907 which made personality encodings indirect, do the same for TType encodings. This fixes the case where a try/catch block needs to generate references to, for example, std::exception in the .gcc_except_table. This commit uses DW_EH_PE_sdata8 for N64 as far as is possible at the moment. However, it is possible to end up with DW_EH_PE_sdata4 when a TargetMachine is not available. There's no risk of issues with inconsistency here since the tables are self describing but it does mean there is a small chance of the PC-relative offset being out of range for particularly large programs. Reviewers: petarj Reviewed By: petarj Subscribers: srhines, joerg, tberghammer, llvm-commits Differential Revision: http://reviews.llvm.org/D9669 llvm-svn: 238190
* Remove most uses of MCSectionData from MCAssembler.Rafael Espindola2015-05-261-1/+1
| | | | llvm-svn: 238172
* Stop using MCSectionData in MCMachObjectWriter.h.Rafael Espindola2015-05-264-34/+20
| | | | llvm-svn: 238165
* Stop using MCSectionData in MCExpr.h.Rafael Espindola2015-05-263-31/+20
| | | | llvm-svn: 238163
* Return a MCSection from MCFragment::getParent().Rafael Espindola2015-05-264-41/+64
| | | | | | Another step in merging MCSectionData and MCSection. llvm-svn: 238162
* Turn MCSectionData into a field of MCSection.Rafael Espindola2015-05-251-1/+1
| | | | | | | This also changes MCAssembler to store a vector of MCSections instead of an iplist of MCSectionData. llvm-svn: 238159
* [X86][AVX2] Vectorized i16 shift operatorsSimon Pilgrim2015-05-252-13/+35
| | | | | | | | Part of D9474, this patch extends AVX2 v16i16 types to 2 x 8i32 vectors and uses i32 shift variable shifts before packing back to i16. Adds AVX2 tests for v8i16 and v16i16 llvm-svn: 238149
* R600/SI: Remove some unnecessary patterns from VINTRP multiclassTom Stellard2015-05-252-11/+9
| | | | | | | DisableEncoding and Constraints can be set using let statements around the multiclass defs. llvm-svn: 238148
* R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chipsTom Stellard2015-05-255-10/+50
| | | | | | The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
* R600/SI: Use NAME rather than opName as the key to the MCOpcode tablesTom Stellard2015-05-252-7/+7
| | | | | | | | This lets us drop a parameter the opName parameter to the VINTRP multiclass and makes it possible to create multiple VINTRP defs with the same asm mnemonic. llvm-svn: 238146
* This patch adds support for the vector quadword add/sub instructions introducedKit Barton2015-05-252-9/+19
| | | | | | | | | | | | | | | | | | | | in POWER8: vadduqm vaddeuqm vaddcuq vaddecuq vsubuqm vsubeuqm vsubcuq vsubecuq In addition to adding the instructions themselves, it also adds support for the v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and IntrinsicEmitter.cpp). http://reviews.llvm.org/D9081 llvm-svn: 238144
* Stop forwarding getOrdinal and setOrdinal.Rafael Espindola2015-05-254-11/+15
| | | | llvm-svn: 238139
* [X86] When pattern-matching scalar FMA3 intrinsics, don't re-arrange the ↵Michael Kuperstein2015-05-251-2/+7
| | | | | | | | | | | | | first and second operands. The semantics of the scalar FMA intrinsics are that the high vector elements are copied from the first source. The existing pattern switches src1 and src2 around, to match the "213" order, which ends up tying the original src2 to the dest. Since the actual scalar fma3 instructions copy the high elements from the dest register, the wrong values are copied. This modifies the pattern to leave src1 and src2 in their original order. Differential Revision: http://reviews.llvm.org/D9908 llvm-svn: 238131
* Added promotion to EXTRACT_SUBVECTOR operand.Elena Demikhovsky2015-05-251-0/+4
| | | | | | | I encountered with this case in one of KNL tests for i1 vectors. v16i1 = EXTRACT_SUBVECTOR v32i1, x llvm-svn: 238130
* Reformat.NAKAMURA Takumi2015-05-252-84/+83
| | | | llvm-svn: 238126
* Prune CRLFs.NAKAMURA Takumi2015-05-255-1546/+1546
| | | | llvm-svn: 238125
* Add target hook to allow merging stores of nonzero constantsMatt Arsenault2015-05-242-0/+10
| | | | | | | | | | On GPU targets, materializing constants is cheap and stores are expensive, so only doing this for zero vectors was silly. Most of the new testcases aren't optimally merged, and are for later improvements. llvm-svn: 238108
* Bump SmallString to the minimum required amount for raw_ostream to avoid ↵Benjamin Kramer2015-05-231-1/+1
| | | | | | | | allocation. NFC. llvm-svn: 238104
* [Mips] Prefer Twine::utohexstr over utohexstr, saves a string copy.Benjamin Kramer2015-05-231-3/+2
| | | | | | NFC. llvm-svn: 238103
* [AArch64] Clean up the ELF streamer a bit.Benjamin Kramer2015-05-232-15/+4
| | | | llvm-svn: 238102
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