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* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-166-62/+185
| | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
* Make sure FABS on v2f32 and v4f32 is legal on ARM NEONAnton Korobeynikov2012-11-162-7/+9
| | | | | | This fixes PR14359 llvm-svn: 168200
* Fix handling of aliases to functions.Richard Osborne2012-11-161-13/+9
| | | | | | An alias to a function should use pc relative addressing. llvm-svn: 168199
* [NVPTX] Order global variables in def-use order before emiting them in the ↵Justin Holewinski2012-11-161-3/+67
| | | | | | final assembly llvm-svn: 168198
* Using const cast to alleviate a warning.Joe Abbey2012-11-161-1/+2
| | | | | | A PR is being filed to address some code issues here. llvm-svn: 168185
* Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.Duncan Sands2012-11-163-5/+63
| | | | llvm-svn: 168166
* Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ↵Craig Topper2012-11-162-0/+68
| | | | | | vector types. llvm-svn: 168141
* [mips] Fix delay slot filler so that instructions with register operand $1 areAkira Hatanaka2012-11-161-17/+34
| | | | | | allowed in branch delay slot. llvm-svn: 168131
* Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman2012-11-151-0/+2
| | | | | | | | case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. llvm-svn: 168107
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-156-11/+16
| | | | | | support and use it in place of HasMips32r2Or64. llvm-svn: 168089
* PowerPC: Lowering floor intrinsic for AltivecAdhemerval Zanella2012-11-152-0/+14
| | | | | | | | This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and llvm.nearbyint to Altivec instruction when using 4 single-precision float vectors. llvm-svn: 168086
* Add assertions in MipsLongBranch which check the size of basic blocks.Akira Hatanaka2012-11-151-1/+7
| | | | llvm-svn: 168078
* Return 0 instead of false.Jakub Staszak2012-11-151-3/+3
| | | | llvm-svn: 168076
* Simplify code.Jakub Staszak2012-11-151-1/+1
| | | | llvm-svn: 168064
* Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko2012-11-153-3/+3
| | | | llvm-svn: 168049
* Revert changing FNEG of v4f32 to Expand. It's legal.Craig Topper2012-11-151-1/+0
| | | | llvm-svn: 168030
* Make FNEG and FABS of v4f32 Expand.Craig Topper2012-11-151-0/+2
| | | | llvm-svn: 168029
* Make a bunch of floating point operations on vectors Expand so that ↵Craig Topper2012-11-151-6/+10
| | | | | | instruction selection won't fail. llvm-svn: 168028
* Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper2012-11-153-1/+13
| | | | llvm-svn: 168025
* Remove unneeded #includes.Jakub Staszak2012-11-141-3/+0
| | | | llvm-svn: 168006
* NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable]NAKAMURA Takumi2012-11-141-6/+4
| | | | llvm-svn: 168001
* Remove the CellSPU port.Eric Christopher2012-11-1452-14677/+1
| | | | | | Approved by Chris Lattner. llvm-svn: 167984
* Fix invalid asserts, use llvm_unreachable instead.Jakub Staszak2012-11-141-3/+3
| | | | llvm-svn: 167976
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-144-233/+187
| | | | llvm-svn: 167974
* X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer2012-11-141-7/+2
| | | | | | | | | | | | | | | | | | bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. llvm-svn: 167967
* The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem2012-11-141-6/+7
| | | | | | | | | | | is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 llvm-svn: 167963
* [NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski2012-11-142-2/+61
| | | | | | | | | Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 llvm-svn: 167948
* X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach2012-11-142-9/+42
| | | | | | | | | | When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
* Set FFLOOR of vectors to expand to keep intruction selection from failing.Craig Topper2012-11-141-0/+1
| | | | llvm-svn: 167922
* Factor out an overly replicated typecast. No functional change.Craig Topper2012-11-141-65/+66
| | | | llvm-svn: 167916
* Set FFLOOR for vectors to expand on CellSPU to keep instruction selection ↵Craig Topper2012-11-141-1/+2
| | | | | | from failing on llvm.floor of a vector. llvm-svn: 167914
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-145-20/+38
| | | | | | | | Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
* Add (some) PowerPC TLS relocation types to ELF.h andUlrich Weigand2012-11-131-2/+18
| | | | | | | generate them from PPCELFObjectWriter::getRelocTypeInner as appropriate. llvm-svn: 167864
* Fix wrong PowerPC instruction opcodes for:Ulrich Weigand2012-11-132-4/+4
| | | | | | | | - lwaux - lhzux - stbu llvm-svn: 167863
* Fix wrong PowerPC instruction encodings due toUlrich Weigand2012-11-132-10/+10
| | | | | | | | | operand field name mismatches in: - AForm_3 (fmul, fmuls) - XFXForm_5 (mtcrf) - XFLForm (mtfsf) llvm-svn: 167862
* Fix instruction encoding for "bd(n)z" on PowerPC,Ulrich Weigand2012-11-133-14/+15
| | | | | | by using a new instruction format BForm_1. llvm-svn: 167861
* Fix instruction encoding for "isel" on PowerPC,Ulrich Weigand2012-11-133-2/+22
| | | | | | using a new instruction format AForm_4. llvm-svn: 167860
* X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren2012-11-131-0/+12
| | | | | | | | | | | chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 llvm-svn: 167859
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-131-0/+4
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
* Test commit.Jyotsna Verma2012-11-131-0/+1
| | | | | | Add a blank line. llvm-svn: 167819
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-0/+6
| | | | | | | | | | This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. llvm-svn: 167742
* Make TOC order deterministic by using MapVector instead of DenseMap.Ulrich Weigand2012-11-121-3/+3
| | | | llvm-svn: 167737
* Remove unused field.Eric Christopher2012-11-121-1/+0
| | | | llvm-svn: 167719
* Fix PR14314Michael Liao2012-11-121-2/+2
| | | | | | | - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. llvm-svn: 167718
* [NVPTX] Add more precise PTX/SM target attributesJustin Holewinski2012-11-124-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. llvm-svn: 167699
* Move some helper methods to being static functions in the implementation file.Craig Topper2012-11-112-20/+7
| | | | llvm-svn: 167696
* Use the isTruncFree and isZExtFree API to figure out of these operations are ↵Nadav Rotem2012-11-111-2/+10
| | | | | | free. Thanks Andy! llvm-svn: 167685
* Remove unnecessary subtraction and addition by 1 around a couple for loops.Craig Topper2012-11-101-6/+6
| | | | llvm-svn: 167673
* Tidy up spacing. No functional change.Craig Topper2012-11-101-4/+4
| | | | llvm-svn: 167671
* Removed unimplemented method declaration.Craig Topper2012-11-101-1/+0
| | | | llvm-svn: 167670
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