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* [mips] Optimize stack pointer adjustments.Simon Dardis2016-06-143-4/+17
| | | | | | | | | | | | | | | | | | | | | Instead of always using addu to adjust the stack pointer when the size out is of the range of an addiu instruction, use subu so that a smaller constant can be generated. This can give savings of ~3 instructions whenever a function has a a stack frame whose size is out of range of an addiu instruction. This change may break some naive stack unwinders. Partially resolves PR/26291. Thanks to David Chisnall for reporting the issue. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21321 llvm-svn: 272666
* [Thumb] Fix off-by-one error in r272007James Molloy2016-06-142-6/+6
| | | | | | | | We can only generate immediates up to #510 with a MOV+ADD, not #511, because there's no such instruction as add #256. Found by Oliver Stannard and csmith! llvm-svn: 272665
* [mips][atomics] Fix atomic instruction descriptions and uses.Simon Dardis2016-06-148-22/+107
| | | | | | | | | | | | | | PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
* [mips][ias] Implement one N32 case (of two) for .cpsetup.Daniel Sanders2016-06-141-28/+27
| | | | | | | | | | | | | | | | | | | | | | This patch implements the N32 case where -mno-shared is in effect. The case where -mshared is in effect will be added later since doing that now requires additional changes to how we handle %hi(%neg(%gp_rel(foo))) expressions to emit the three relocations as three relocations (currently only one of the three would be emitted) which then requires further changes to our MCFixup handling. While we could fix both cases together, fixing the -mno-shared case allows us to fix the ELFCLASS bug (where N32 incorrectly uses ELFCLASS64 instead of ELFCLASS32) in a way that allows cpsetup.s to check for a correct output instead of another incorrect output. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21131 llvm-svn: 272652
* [X86][SSE4A] Added patterns for nontemporal stores of scalar float/doubles ↵Simon Pilgrim2016-06-141-2/+12
| | | | | | using MOVNTSD/MOVNTSS llvm-svn: 272651
* [mips] MIPS32/64 itinerariesSimon Dardis2016-06-147-125/+300
| | | | | | | | | | | Itineraries for some pre MIPSR6 and EVA instructions. Some pseudo expanded instructions are marked as having no scheduling info. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D20418 llvm-svn: 272648
* [mips][dsp] Fix use without def on DSPCtrl registers read by rddsp intrinsic.Daniel Sanders2016-06-141-1/+2
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21063 llvm-svn: 272647
* [mips][msa] copyPhysReg() should not set RegState::Define on result of CTCMSA.Daniel Sanders2016-06-141-2/+5
| | | | | | | | | | | | | | Summary: The machine verifier reports 'Explicit operand marked as def' when it is manually specified even though it agrees with the operand info. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21065 llvm-svn: 272646
* [AVX512] Use AND32ri8 instead of AND32ri when anding with 1 to create single ↵Craig Topper2016-06-141-9/+9
| | | | | | bit masks. This results in a smaller encoding. llvm-svn: 272627
* [AVX512] Use MOVZX32 instead of MOVZ16 for loading single v8/v4/v2/v1 masks ↵Craig Topper2016-06-141-4/+4
| | | | | | when KMOVB is not available. This has better behavior with respect to partial register stalls since it won't need to preserve the upper 16-bits of the GPR. llvm-svn: 272626
* [AVX512] Add patterns for zero-extending a mask that use the def of ↵Craig Topper2016-06-141-0/+6
| | | | | | KMOVW/KMOVB without going through an EXTRACT_SUBREG and a MOVZX. llvm-svn: 272625
* Update the AArch64ExternalSymbolizer to print literal strings as escaped stringsKevin Enderby2016-06-131-3/+5
| | | | | | | | so it is the same as the MCExternalSymbolizer. rdar://17349181 llvm-svn: 272588
* [X86] Remove llvm.x86.bit.scan.{forward,reverse}.32David Majnemer2016-06-131-2/+0
| | | | | | | The need for these intrinsics has been obviated by r272564 which reimplements their functionality using generic IR. llvm-svn: 272566
* AMDGPU/SI: Set INDEX_STRIDE for scratch coalescingMarek Olsak2016-06-132-3/+6
| | | | | | | | | | | | | | | | | Summary: Mesa and other users must set this to enable coalescing: - STRIDE = 0 - SWIZZLE_ENABLE = 1 This makes one particular compute shader 8x faster. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21136 llvm-svn: 272556
* AMDGPU: Fix post-RA verifier errors with trackLivenessAfterRegAllocMatt Arsenault2016-06-131-14/+16
| | | | | | | The condition reg of the cndmask_b64 expansion can't be killed by the first one, and the implicit super register implicit def is needed. llvm-svn: 272554
* [SystemZ] Enable index register memory constraints for inline ASMUlrich Weigand2016-06-132-27/+25
| | | | | | | | | | | | | | | | This enables use of the 'R' and 'T' memory constraints for inline ASM operands on SystemZ, which allow an index register as well as an immediate displacement. This patch includes corresponding documentation and test case updates. As with the last patch of this kind, I moved the 'm' constraint to the most general case, which is now 'T' (base + 20-bit signed displacement + index register). Author: colpell Differential Revision: http://reviews.llvm.org/D21239 llvm-svn: 272547
* [ARM] Reverting r272544 because clang patch needsRanjeet Singh2016-06-133-64/+13
| | | | | | | to go in as soon as llvm patch has gone in because tests will start breaking in Clang. llvm-svn: 272546
* [ARM] Add mrrc/mrrc2 co-processor intrinsicsRanjeet Singh2016-06-133-13/+64
| | | | | | | | | | | | | MRRC/MRRC2 instruction writes to two registers. The intrinsic definition returns a single uint64_t to represent the write, this is a compact way of representing a write to two 32 bit registers, the alternative might have been two return a struct of 2 uint32_t's but this isn't as nice. Differential Revision: llvm-svn: 272544
* Fix an enumeral mismatch warning.Haojian Wu2016-06-131-2/+4
| | | | | | | | | | | | | | | | | Summary: The "-Werror=enum-compare" shows that the statement is using two different enums: enumeral mismatch in conditional expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType' A follow-up fix on D21235. Reviewers: klimek Subscribers: spatel, cfe-commits Differential Revision: http://reviews.llvm.org/D21278 llvm-svn: 272539
* [AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and ↵Craig Topper2016-06-131-18/+0
| | | | | | autoupgrade them to selects and shufflevector. llvm-svn: 272527
* Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2016-06-1210-11/+11
| | | | | | No functionality change intended. llvm-svn: 272516
* Move instances of std::function.Benjamin Kramer2016-06-125-15/+15
| | | | | | Or replace with llvm::function_ref if it's never stored. NFC intended. llvm-svn: 272513
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-12123-1702/+1485
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [x86, SSE] change patterns for CMPP to float types to allow matching with ↵Sanjay Patel2016-06-123-23/+53
| | | | | | | | | | | | | | | | | | | | | | | | | SSE1 (PR28044) This patch is intended to solve: https://llvm.org/bugs/show_bug.cgi?id=28044 By changing the definition of X86ISD::CMPP to use float types, we allow it to be created and pass legalization for an SSE1-only target where v4i32 is not legal. The motivational trail for this change includes: https://llvm.org/bugs/show_bug.cgi?id=28001 and eventually makes this trigger: http://reviews.llvm.org/D21190 Ie, after this step, we should be free to have Clang generate FP compare IR instead of x86 intrinsics for SSE C packed compare intrinsics. (We can auto-upgrade and remove the LLVM sse.cmp intrinsics as a follow-up step.) Once we're generating vector IR instead of x86 intrinsics, a big pile of generic optimizations can trigger. Differential Revision: http://reviews.llvm.org/D21235 llvm-svn: 272511
* [X86] Remove sse2 pshufd/pshuflw/pshufhw intrinsics and upgrade them to ↵Craig Topper2016-06-121-3/+0
| | | | | | shufflevector. llvm-svn: 272510
* [AVX512] Remove the masked palignr intrinsics that I forgot to remove when I ↵Craig Topper2016-06-121-6/+0
| | | | | | added auto-upgrade code to turn them into shufflevectors and selects. llvm-svn: 272497
* [CostModel][X86][SSE] Updated costs for vector BITREVERSE ops on SSSE3+ targetsSimon Pilgrim2016-06-111-0/+30
| | | | | | To account for the fast PSHUFB implementation now available llvm-svn: 272484
* [X86][SSSE3] Added PSHUFB LUT implementation of BITREVERSESimon Pilgrim2016-06-111-2/+60
| | | | | | PSHUFB can speed up BITREVERSE of byte vectors by performing LUT on the low/high nibbles separately and ORing the results. Wider integer vector types are already BSWAP'd beforehand so also make use of this approach. llvm-svn: 272477
* Strip trailing whitespace. NFCI.Simon Pilgrim2016-06-111-55/+55
| | | | llvm-svn: 272476
* [AVX512] Lower v8i64 and v16i32 to pshufd when possible.Craig Topper2016-06-111-4/+35
| | | | llvm-svn: 272473
* [X86][SSE] Added PSLLDQ/PSRLDQ as a target shuffle typeSimon Pilgrim2016-06-111-0/+17
| | | | | | Ensure that PALIGNR/PSLLDQ/PSRLDQ are byte vectors so that they can be correctly decoded for target shuffle combining llvm-svn: 272471
* [X86][SSE] Use vXi8 return type for PSLLDQ/PSRLDQ instructionsSimon Pilgrim2016-06-113-20/+22
| | | | | | These are byte shift instructions and it will make shuffle combining a lot more straightforward if we can assume a vXi8 vector of bytes so decoded shuffle masks match the return type's number of elements llvm-svn: 272468
* [X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment ↵Simon Pilgrim2016-06-111-35/+17
| | | | | | | | generation Now matches other shuffles llvm-svn: 272464
* Try a bit harder to remove the signed and unsigned comparison warning.Chandler Carruth2016-06-111-1/+1
| | | | | | Hopefully this time it actually works and stays away. llvm-svn: 272463
* Compare to an unsigned literal to avoid a -Wsign-compare warning.Chandler Carruth2016-06-111-1/+1
| | | | llvm-svn: 272459
* [AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This ↵Craig Topper2016-06-111-0/+11
| | | | | | allows us to create 512-bit PSHUFLW/PSHUFHW. llvm-svn: 272450
* [AVX512] No need to check for BWI being enabled before lowering v32i16 and ↵Craig Topper2016-06-111-9/+2
| | | | | | v64i8 shuffles. If we get this far the types are already legal which means BWI must be enabled. llvm-svn: 272449
* [STLExtras] Introduce and use llvm::count_if; NFCSanjoy Das2016-06-101-21/+12
| | | | | | (This is split out from was D21115) llvm-svn: 272435
* [AArch64] Move comments closer to relevant check. NFC.Chad Rosier2016-06-101-6/+4
| | | | llvm-svn: 272430
* [AArch64] Refactor a check earlier. NFC.Chad Rosier2016-06-101-12/+18
| | | | llvm-svn: 272429
* [x86] enable bitcasted fabs/fneg transformsSanjay Patel2016-06-101-0/+4
| | | | | | | The vector cases don't change because we already have folds in X86ISelLowering to look through and remove bitcasts. llvm-svn: 272427
* Remove a few gendered pronouns.Nico Weber2016-06-101-1/+1
| | | | llvm-svn: 272422
* [SystemZ] Support Compare and TrapsZhan Jun Liau2016-06-108-44/+193
| | | | | | | | | | | | Support and generate Compare and Traps like CRT, CIT, etc. Support Trap as legal DAG opcodes and generate "j .+2" for them by default. Add support for Conditional Traps and use the If Converter to convert them into the corresponding compare and trap opcodes. Differential Revision: http://reviews.llvm.org/D21155 llvm-svn: 272419
* AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocationsTom Stellard2016-06-102-1/+7
| | | | | | | | | | | | | | | Summary: We need to set the fixup type to FK_Data_4 for the SCRATCH_RSRC_DWORD[01] symbols, since these require absolute relocations, and fixup_si_rodata is for relative relocations. Reviewers: arsenm, kzhuravl Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21153 llvm-svn: 272417
* [X86] Add costs for SSE zext/sext to v4i64 to TTIMichael Kuperstein2016-06-101-0/+14
| | | | | | | | | The costs are somewhat hand-wavy, but should be much closer to the truth than what we get from BasicTTI. Differential Revision: http://reviews.llvm.org/D21156 llvm-svn: 272406
* [AArch64] Add preferred alignments for Exynos M1Evandro Menezes2016-06-103-2/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D21203 llvm-svn: 272400
* [Hexagon] Remove incorrect offset scalingKrzysztof Parzyszek2016-06-101-4/+2
| | | | llvm-svn: 272399
* Test commitRoman Shirokiy2016-06-101-3/+3
| | | | llvm-svn: 272393
* [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning ↵Sam Kolton2016-06-105-257/+348
| | | | | | | | | | | | | | | | | | in AMDGPUOperand. Summary: sext() modifier is supported in SDWA instructions only for integer operands. Spec is unclear should integer operands support abs and neg modifiers with sext - for now they are not supported. Renamed InputModsWithNoDefault to FloatInputMods. Added SextInputMods for operands that support sext() modifier. Added AMDGPUOperand::Modifier struct to handle register and immediate modifiers. Code cleaning in AMDGPUOperand class: organize method in groups (render-, predicate-methods...). Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20968 llvm-svn: 272384
* test commit: remove trailing whitespaces in README.txtRoger Ferrer Ibanez2016-06-101-8/+8
| | | | llvm-svn: 272380
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