summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* whitespaceAndrew Trick2011-10-182-7/+7
| | | | llvm-svn: 142394
* A landing pad could have more than one predecessor. In that case, we want thatBill Wendling2011-10-181-1/+8
| | | | | | | | | | predecessor to remove the jump to it as well. Delay clearing the 'landing pad' flag until after the jumps have been removed. (There is an implicit assumption in several modules that an MBB which jumps to a landing pad has only two successors.) <rdar://problem/10304224> llvm-svn: 142390
* ARM vmla/vmls assembly parsing for the lane index operand.Jim Grosbach2011-10-181-8/+8
| | | | llvm-svn: 142389
* ARM vqdmulh assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142386
* ARM vmul assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142381
* Final patch that completes old JIT support for Mips:Bruno Cardoso Lopes2011-10-187-91/+173
| | | | | | | | | | | | | | | | -Fix binary codes and rename operands in .td files so that automatically generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct encoding for instructions. -Define new class FMem for instructions that access memory. -Define new class FFRGPR for instructions that move data between GPR and FPU general and control registers. -Define custom encoder methods for memory operands, and also for size operands of ext and ins instructions. -Only static relocation model is currently implemented. Patch by Sasa Stankovic llvm-svn: 142378
* Fix incorrect check for sign-extended constant BUILD_VECTOR.Bob Wilson2011-10-181-1/+1
| | | | | | <rdar://problem/10298332> llvm-svn: 142371
* ARM vqdmlal assembly parsing for the lane index operand.Jim Grosbach2011-10-181-2/+2
| | | | llvm-svn: 142365
* Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.Jim Grosbach2011-10-181-0/+2
| | | | llvm-svn: 142363
* ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach2011-10-182-2/+32
| | | | llvm-svn: 142356
* PTX: Fix disabling of MAD instruction selectionJustin Holewinski2011-10-181-7/+14
| | | | llvm-svn: 142352
* Fix a bunch of unused variable warnings when doing a releaseDuncan Sands2011-10-183-8/+7
| | | | | | build with gcc-4.6. llvm-svn: 142350
* Coding style cleanups. No functionality change.Bill Wendling2011-10-181-6/+5
| | | | llvm-svn: 142341
* Remove NaClModeDavid Meyer2011-10-1810-42/+4
| | | | llvm-svn: 142338
* Add support for dynamic stack realignment when in thumb1 mode.Chad Rosier2011-10-183-11/+32
| | | | | | rdar://10288916 llvm-svn: 142337
* Commit test, capitalizing store... keep it simple.Joe Abbey2011-10-181-1/+1
| | | | llvm-svn: 142336
* Fix misc warnings. Patch by Joe Abbey.Eli Friedman2011-10-183-4/+1
| | | | llvm-svn: 142332
* Backing out patch. Will refactor to remove the AsmParser dependency on Target.Lang Hames2011-10-181-88/+25
| | | | llvm-svn: 142323
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach2011-10-182-8/+77
| | | | llvm-svn: 142321
* Re-applying the target data layout verification patch from r142288, plus ↵Lang Hames2011-10-171-25/+88
| | | | | | | | appropriate CMake dependencies. Thanks to Raphael Espindola for tracking down the CMake issues. llvm-svn: 142306
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach2011-10-172-8/+36
| | | | llvm-svn: 142303
* Add support for a new extension to the .file directive:Nick Lewycky2011-10-174-7/+20
| | | | | | | | | | .file filenumber "directory" "filename" This removes one join+split of the directory+filename in MC internals. Because bitcode files have independent fields for directory and filenames in debug info, this patch may change the .o files written by existing .bc files. llvm-svn: 142300
* Add a few FIXME comments.Chad Rosier2011-10-171-0/+2
| | | | llvm-svn: 142299
* Tidy up.Jim Grosbach2011-10-171-1/+0
| | | | llvm-svn: 142297
* 142288 broke the build:Rafael Espindola2011-10-171-88/+25
| | | | | | | | | | | | Linking CXX executable ../../bin/llvm-as ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' clang-3: error: linker command failed with exit code 1 (use -v to see invocation) Revert "Validate target data layout strings." This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e. llvm-svn: 142296
* Now Igor, throw the switch...give my creation life!Bill Wendling2011-10-173-4/+8
| | | | | | | | | | | | | | | | | Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> llvm-svn: 142294
* ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach2011-10-172-3/+45
| | | | | | | | NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. llvm-svn: 142293
* Validate target data layout strings.Lang Hames2011-10-171-25/+88
| | | | | | Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion. llvm-svn: 142288
* Use a SmallVector for intrinsic argument types.Benjamin Kramer2011-10-172-2/+2
| | | | llvm-svn: 142259
* Don't renumber the blocks here. This could cause problems later on if anotherBill Wendling2011-10-171-3/+1
| | | | | | pass renumbers the blocks again. llvm-svn: 142258
* Pseudoinstructions should not be less constrained than the instruction they areCameron Zwarich2011-10-171-6/+6
| | | | | | lowered to. This fixes a lot of verifier failures on the test suite. llvm-svn: 142254
* Tidy up organization.Jim Grosbach2011-10-171-8/+4
| | | | llvm-svn: 142248
* Add a call to EmitSjLjDispatchBlock.Bill Wendling2011-10-171-0/+8
| | | | | | | Once the intrinsics are marked as having a custom inserter, it will call this method to emit the dispatch table into the machine function. llvm-svn: 142245
* Fix improperly formed assert() call.Jim Grosbach2011-10-171-1/+1
| | | | llvm-svn: 142239
* Add definitions of conditional moves with 64-bit operands. Comment out code forAkira Hatanaka2011-10-173-75/+130
| | | | | | | expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
* Revert change to function alignment b/c existing logic was fineHal Finkel2011-10-171-10/+3
| | | | llvm-svn: 142224
* Removed set, but unused variables.Chad Rosier2011-10-172-12/+0
| | | | | | Patch by Joe Abbey <jabbey@arxan.com>. llvm-svn: 142223
* Move class and instruction definitions for conditional moves to a seperate file.Akira Hatanaka2011-10-174-106/+112
| | | | llvm-svn: 142220
* Revert change made in r142205.Akira Hatanaka2011-10-171-2/+2
| | | | llvm-svn: 142217
* Redefine count-leading 0s and 1s instructions.Akira Hatanaka2011-10-172-20/+17
| | | | llvm-svn: 142216
* Redefine mfhi/lo and mthi/lo instructions.Akira Hatanaka2011-10-172-35/+16
| | | | llvm-svn: 142214
* Redefine multiply and divide instructions.Akira Hatanaka2011-10-172-25/+26
| | | | llvm-svn: 142211
* Add definition of a base class for logical shift/rotate instructions with twoAkira Hatanaka2011-10-172-20/+12
| | | | | | source registers and redefine 32-bit and 64-bit instructions. llvm-svn: 142210
* Remove >80-col line and unicodeHal Finkel2011-10-171-2/+2
| | | | llvm-svn: 142209
* Add definition of a base class for logical shift/rotate immediate instructionsAkira Hatanaka2011-10-172-27/+33
| | | | | | and have 32-bit and 64-bit instructions derive from it. llvm-svn: 142207
* Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.Akira Hatanaka2011-10-173-9/+11
| | | | llvm-svn: 142205
* Fix CMake build.Michael J. Spencer2011-10-171-1/+0
| | | | llvm-svn: 142204
* svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cppDevang Patel2011-10-172-220/+2
| | | | | | There is no reason to have simple IR level pass in lib/Target. llvm-svn: 142200
* Instructions for Book E PPC should be word aligned, set function alignment ↵Hal Finkel2011-10-171-3/+10
| | | | | | to reflect this llvm-svn: 142194
* Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means ↵Craig Topper2011-10-172-24/+19
| | | | | | that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. llvm-svn: 142177
OpenPOWER on IntegriCloud