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* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-031-1/+51
| | | | llvm-svn: 274464
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-031-0/+56
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-0/+34
| | | | llvm-svn: 274461
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-031-2/+53
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
* [X86][AVX512] Add support for lowering shuffles to VPERMILPSSimon Pilgrim2016-07-031-0/+4
| | | | llvm-svn: 274458
* Fix spelling.Simon Pilgrim2016-07-021-2/+2
| | | | llvm-svn: 274451
* [X86][AVX512] Add support for lowering shuffles to VPERMILPDSimon Pilgrim2016-07-021-0/+11
| | | | llvm-svn: 274450
* [X86][AVX512] Add support for 512-bit PSHUFB loweringSimon Pilgrim2016-07-021-2/+7
| | | | llvm-svn: 274444
* [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to ↵Simon Pilgrim2016-07-021-18/+0
| | | | | | generic IR llvm-svn: 274443
* [Hexagon] Create global std::map lazily.Benjamin Kramer2016-07-021-3/+3
| | | | | | | | This could of course be a simple binary search with no global state involved at all if someone cares enough. Just don't make everyone linking the hexagon backend pay for it on process startup and shutdown. llvm-svn: 274437
* [X86][AVX512] Add support for lowering shuffles to MOVDDUP/MOVSLDUP/MOVSHDUPSimon Pilgrim2016-07-021-0/+19
| | | | llvm-svn: 274436
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-027-44/+24
| | | | | | | | where possible. No functionality change intended. llvm-svn: 274431
* [SystemZ] Move misplaced SystemZ::TDC to non-memory opcode range.Marcin Koscielnicki2016-07-022-7/+7
| | | | llvm-svn: 274417
* AMDGPU: Add feature for unaligned accessMatt Arsenault2016-07-015-12/+32
| | | | llvm-svn: 274398
* AMDGPU: Expand unaligned accesses earlyMatt Arsenault2016-07-012-21/+48
| | | | | | | | Due to visit order problems, in the case of an unaligned copy the legalized DAG fails to eliminate extra instructions introduced by the expansion of both unaligned parts. llvm-svn: 274397
* AMDGPU: Improve load/store of illegal types.Matt Arsenault2016-07-013-113/+102
| | | | | | | | | | There was a combine before to handle the simple copy case. Split this into handling loads and stores separately. We might want to change how this handles some of the vector extloads, since this can result in large code size increases. llvm-svn: 274394
* [Hexagon] Revert r274381: that was actually wrongKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274384
* [Hexagon] Use MachineOperand::readsReg instead of isUseKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274381
* AMDGPU/SI: Enable testing several variants for si schedulerMatt Arsenault2016-07-011-2/+2
| | | | | | | | | | Enable testing different scheduling variants if sgpr usage is very high. It was previously disabled because of a bug in handleMove, but it has been fixed since. Patch by Axel Davy llvm-svn: 274372
* Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs"Hans Wennborg2016-07-011-144/+327
| | | | | | This caused PR28387: Assertion "#operands for dag node doesn't match .td file!" llvm-svn: 274367
* Do not count debug instructions when counting number of uses to reorder ↵Dehao Chen2016-07-011-0/+2
| | | | | | | | | | | | | | frame objects. Summary: The code generation should be independent of the debug info. Reviewers: zansari, davidxl, mkuper, majnemer Subscribers: majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D21911 llvm-svn: 274357
* [ARM] Refactor Thumb2 mul instruction descsSam Parker2016-07-011-327/+144
| | | | | | | | | No functional changes. Just created wrapper classes around the 3 and 4 reg mult and mac instruction classes. Differential Revision: http://reviews.llvm.org/D21549 llvm-svn: 274347
* Resubmit r268719 - AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.Nikolay Haustov2016-07-012-5/+10
| | | | | | | | | | | | | | | | | | | This was reverted in r268740 because of problems with corresponding Clang change. Clang change was updated and resubmitted in r274220. Check calling convention in AMDGPUMachineFunction::isKernel This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19917 llvm-svn: 274341
* [AMDGPU] Assembler: support SDWA for VOPC instructionsSam Kolton2016-07-013-45/+113
| | | | | | | | | | | | Summary: dst_sel and dst_unused disabled for VOPC as they have no effect on result Reviewers: artem.tamazov, tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21376 llvm-svn: 274340
* Update libdeps; AMDGPUCodeGen requires LLVMVectorize.NAKAMURA Takumi2016-07-011-1/+1
| | | | llvm-svn: 274339
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-013-31/+32
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
* AMDGPU: Add option to run the load/store vectorizerMatt Arsenault2016-07-011-0/+16
| | | | llvm-svn: 274329
* CodeGen: Use MachineInstr& in LiveVariables API, NFCDuncan P. N. Exon Smith2016-07-013-11/+11
| | | | | | | | | Change all the methods in LiveVariables that expect non-null MachineInstr* to take MachineInstr& and update the call sites. This clarifies the API, and designs away a class of iterator to pointer implicit conversions. llvm-svn: 274319
* AMDGPU: Implement getLoadStoreVecRegBitWidthMatt Arsenault2016-07-012-0/+23
| | | | llvm-svn: 274312
* Target: Remove unused arguments from overrideSchedPolicy, NFCDuncan P. N. Exon Smith2016-07-016-11/+2
| | | | | | | | | | TargetSubtargetInfo::overrideSchedPolicy takes two MachineInstr* arguments (begin and end) that invite implicit conversions from MachineInstrBundleIterator. One option would be to change their type to an iterator, but since they don't seem to have been used since the API was added in 2010, I'm deleting the dead code. llvm-svn: 274304
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-3031-1245/+1326
| | | | | | | | | | | | | This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
* Test commit.David L Kreitzer2016-06-301-1/+1
| | | | llvm-svn: 274284
* AMDGPU: Add m0 vgpr load loop block as successorMatt Arsenault2016-06-301-0/+1
| | | | | | | This shows up as a verifier error when I move this earlier, not sure why it didn't before. llvm-svn: 274275
* Delete MCCodeGenInfo.Rafael Espindola2016-06-3016-212/+37
| | | | | | | MC doesn't really care about CodeGen stuff, so this was just complicating target initialization. llvm-svn: 274258
* Test commitElliot Colp2016-06-301-1/+1
| | | | llvm-svn: 274232
* Don't repeat names in comments. NFC.Rafael Espindola2016-06-301-4/+3
| | | | llvm-svn: 274226
* Delete unused includes. NFC.Rafael Espindola2016-06-3011-11/+0
| | | | llvm-svn: 274225
* [SystemZ] Let z13 also support FeatureMiscellaneousExtensions.Jonas Paulsson2016-06-301-0/+1
| | | | | | | | | | | This processor feature had been left out by mistake from the z13 ProcessorModel. This time with updated test case. Thanks, Hans. Reviewed by Ulrich Weigand. llvm-svn: 274216
* [AArch64] Add Broadcom Vulcan scheduling model.Pankaj Gode2016-06-303-4/+863
| | | | | | | | Adding scheduling model for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21728 llvm-svn: 274213
* Use ShuffleVectorSDNode::isSplat member method instead of static method ↵Craig Topper2016-06-302-3/+2
| | | | | | isSplatMask where the mask came directly from getMask() on a shuffle node. llvm-svn: 274208
* [SystemZ] Split up PerformDAGCombine. [NFC]Marcin Koscielnicki2016-06-302-142/+183
| | | | | | This function is already a bit too long, and I'm about to make it worse. llvm-svn: 274191
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-3069-2947/+2926
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Revert r273313 "[NVPTX] Improve lowering of byval args of device functions."Artem Belevich2016-06-293-79/+15
| | | | | | The change causes llvm crash in some unoptimized builds. llvm-svn: 274163
* Permit memory operands in ins/outs instructionsNirav Dave2016-06-291-4/+6
| | | | | | | | | | | | | | | [x86] (PR15455) While (ins|outs)[bwld] instructions do not take %dx as a memory operand, various unofficial references do and objdump disassembles to this format. Extend special treatment of similar (in|out)[bwld] operations. Reviewers: craig.topper, rnk, ab Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18837 llvm-svn: 274152
* Revert r272251, it caused PR28348.Nico Weber2016-06-291-40/+1
| | | | llvm-svn: 274141
* [X86] Lower blended PACKUSes using appropriate types.Ahmed Bougacha2016-06-291-11/+14
| | | | | | | | | | | | | When lowering two blended PACKUS, we used to disregard the types of the PACKUS inputs, indiscriminately generating a v16i8 PACKUS. This leads to non-selectable things like: (v16i8 (PACKUS (v4i32 v0), (v4i32 v1))) Instead, check that the PACKUSes have the same type, and use that as the final result type. llvm-svn: 274138
* Drop support for creating $stubs.Rafael Espindola2016-06-2910-288/+18
| | | | | | They are created by ld64 since OS X 10.5. llvm-svn: 274130
* [SystemZ] Add floating-point test data class instructions.Marcin Koscielnicki2016-06-295-0/+29
| | | | | | | These are not used by CodeGen yet - ISD combiners creating the new node will come in subsequent patches. llvm-svn: 274108
* [ARM] Fix 28282: cost computation for constant hoistingWeiming Zhao2016-06-281-1/+1
| | | | | | | | | | | | | | | | | Summary: This fixes bug: https://llvm.org/bugs/show_bug.cgi?id=28282 Currently the cost model of constant hoisting checks the bit width of the data type of the constants. However, the actual immediate value is small enough and not need to be hoisted. This patch checks for the actual bit width needed for the constant. Reviewers: t.p.northover, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21668 llvm-svn: 274073
* Relax the clearance calculating for breaking partial register dependency.Dehao Chen2016-06-281-6/+16
| | | | | | | | | | | | Summary: LLVM assumes that large clearance will hide the partial register spill penalty. But in our experiment, 16 clearance is too small. As the inserted XOR is normally fairly cheap, we should have a higher clearance threshold to aggressively insert XORs that is necessary to break partial register dependency. Reviewers: wmi, davidxl, stoklund, zansari, myatsina, RKSimon, DavidKreitzer, mkuper, joerg, spatel Subscribers: davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D21560 llvm-svn: 274068
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