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* Fix shouldAssumeDSOLocal for private linkage.Rafael Espindola2016-05-251-1/+1
| | | | llvm-svn: 270746
* AMDGPU: Fix v2i64/v2f64 bitcastsMatt Arsenault2016-05-251-0/+2
| | | | | | | These operations tend to get promoted away to v4i32 so this doesn't happen often. llvm-svn: 270740
* AMDGPU: Fix inconsistent lowering of select of vectorsMatt Arsenault2016-05-251-1/+9
| | | | | | | | | f32 vectors would use a sequence of BFI instructions instead of unrolled cmp + select. This was better in the case of a VALU select with SGPR inputs, but we don't have a way of dealing with that in the DAG. llvm-svn: 270731
* [x86] avoid code explosion from LoopVectorizer for gather loop (PR27826) Sanjay Patel2016-05-251-2/+10
| | | | | | | | | | | | | | By making pointer extraction from a vector more expensive in the cost model, we avoid the vectorization of a loop that is very likely to be memory-bound: https://llvm.org/bugs/show_bug.cgi?id=27826 There are still bugs related to this, so we may need a more general solution to avoid vectorizing obviously memory-bound loops when we don't have HW gather support. Differential Revision: http://reviews.llvm.org/D20601 llvm-svn: 270729
* [x86, AVX] allow explicit calls to VZERO* to modify state in ↵Sanjay Patel2016-05-251-6/+7
| | | | | | | | | | VZeroUpperInserter pass (PR27823) As noted in the review, there are still problems, so this doesn't the bug completely. Differential Revision: http://reviews.llvm.org/D20529 llvm-svn: 270718
* [X86][SSE] Replace (V)CVTDQ2PD(Y) and (V)CVTPS2PD(Y) lossless conversion ↵Simon Pilgrim2016-05-251-29/+15
| | | | | | | | | | intrinsics with generic IR Followup to D20528 clang patch, this removes the (V)CVTDQ2PD(Y) and (V)CVTPS2PD(Y) llvm intrinsics and auto-upgrades to sitofp/fpext instead. Differential Revision: http://reviews.llvm.org/D20568 llvm-svn: 270678
* [X86] Remove the llvm.x86.sse2.storel.dq intrinsic. It hasn't been used in a ↵Craig Topper2016-05-251-7/+0
| | | | | | long time. llvm-svn: 270677
* Soften assertion in AMDGPU emitPrologue.Nirav Dave2016-05-251-2/+3
| | | | | | | | | | | | | | [AMDGPU] emitPrologue looks for an unused unallocated SGPR that is not the scratch descriptor. Continue search if unused register found fails other requirements. Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D20526 llvm-svn: 270646
* [WebAssembly] Put __stack_pointer in the offset field of loads and stores.Dan Gohman2016-05-241-10/+10
| | | | | | | | | | | | | | | | | | | | Instead of this: i32.const $push10=, __stack_pointer i32.load $push11=, 0($pop10) Emit this: i32.const $push10=, 0 i32.load $push11=, __stack_pointer($pop10) It's not currently clear which is better, though there's a chance the second form may be better at overall compression. We can revisit this when we have more data; for now it makes sense to make PEI consistent with isel. Differential Revision: http://reviews.llvm.org/D20411 llvm-svn: 270635
* [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov2016-05-247-23/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D20081 llvm-svn: 270594
* [AMDGPU] Assembler: rework parsing of optional operands.Sam Kolton2016-05-242-282/+86
| | | | | | | | | | | | | | | Summary: Change process of parsing of optional operands. All optional operands use same parsing method - parseOptionalOperand(). No default values are added to OperandsVector. Get rid of WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS. Reviewers: tstellarAMD, vpykhtin, artem.tamazov, nhaustov Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20527 llvm-svn: 270556
* [AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.Artem Tamazov2016-05-243-44/+116
| | | | | | Differential Revision: http://reviews.llvm.org/D20476 llvm-svn: 270552
* [llvm][AVX512][intrinsics] Fix vperm{b|w|d|q|ps|pd} intrinsics. Index is ↵Igor Breger2016-05-242-15/+39
| | | | | | | | second argument to buildin function but it is first instruction operand. Differential Revision: http://reviews.llvm.org/D20515 llvm-svn: 270548
* [MIPS][LLVM-MC] Fix Disassemble of Negative OffsetSagar Thakur2016-05-241-8/+8
| | | | | | | | | | | Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
* [CostModel][X86][XOP] Added XOP costmodel for BITREVERSE Simon Pilgrim2016-05-242-1/+49
| | | | | | Now that we have a nice fast VPPERM solution. Added framework for future intrinsic costs as well. llvm-svn: 270537
* [WebAssembly] Basic TargetTransformInfo support for SIMD128.Dan Gohman2016-05-232-1/+65
| | | | llvm-svn: 270508
* [SPARC] Fix 8 and 16-bit atomic load and store.James Y Knight2016-05-232-14/+22
| | | | | | | | | They were accidentally using the 32-bit load/store instruction for 8/16-bit operations, due to incorrect patterns (8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes) llvm-svn: 270486
* fix typo; NFCSanjay Patel2016-05-231-1/+1
| | | | llvm-svn: 270469
* use range-loop; NFCISanjay Patel2016-05-231-4/+2
| | | | llvm-svn: 270467
* [WebAssembly] Speed up LiveIntervals updating.Dan Gohman2016-05-231-6/+9
| | | | | | | | Use the more specific LiveInterval::removeSegment instead of LiveInterval::shrinkToUses when we know the specific range that's being removed. llvm-svn: 270463
* [Hexagon] Move some debug-only variable declarations into DEBUGKrzysztof Parzyszek2016-05-231-19/+21
| | | | llvm-svn: 270459
* Removing a switch statement that contains only a default label; NFC.Aaron Ballman2016-05-231-3/+1
| | | | llvm-svn: 270444
* [BPF] Remove exit-on-error flag in test (PR27766)Diana Picus2016-05-232-4/+10
| | | | | | | | | | | | | | The exit-on-error flag on the many_args1.ll test is needed to avoid an unreachable in BPFTargetLowering::LowerCall. We can also avoid it by ignoring any superfluous arguments to the call (i.e. any arguments after the first 5). Fixes PR27766. Differential Revision: http://reviews.llvm.org/D20471 v2 of r270419 llvm-svn: 270440
* Reverts "[BPF] Remove exit-on-error flag in test (PR27766)"Renato Golin2016-05-232-8/+4
| | | | | | | | This patch reverts r270419 because it broke a lot of buildbots, mostly Windows. We'd like help in investigating the issues, but for now, it should stay out. llvm-svn: 270433
* [BPF] Remove exit-on-error flag in test (PR27766)Diana Picus2016-05-232-4/+8
| | | | | | | | | | The exit-on-error flag on the many_args1.ll test is needed to avoid an unreachable in BPFTargetLowering::LowerCall. We can also avoid it by ignoring any superfluous arguments to the call (i.e. any arguments after the first 5). Fixes PR27766 llvm-svn: 270419
* [Sparc] LEON erratum fix - Delay Slot Filler modification.Chris Dewhurst2016-05-231-0/+9
| | | | | | This code should have been with the previous check-in (r270417) and prevents the DelaySlotFiller pass being utilized in functions where the erratum fix has been applied as this will break the run-time code. llvm-svn: 270418
* [Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction.Chris Dewhurst2016-05-2310-9/+152
| | | | | | | | | | Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix. The code will have no effect for other Sparc, but non-LEON processors. Differential Review: http://reviews.llvm.org/D20353 llvm-svn: 270417
* [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow ↵Sam Kolton2016-05-232-175/+245
| | | | | | | | | | | | modifiers for imms. Reviewers: nhaustov, tstellarAMD Subscribers: kzhuravl, arsenm Differential Revision: http://reviews.llvm.org/D20166 llvm-svn: 270415
* Test commitJacob Baungard Hansen2016-05-231-1/+0
| | | | llvm-svn: 270414
* [X86] Use instruction aliases to replace custom asm parser code for ↵Craig Topper2016-05-233-51/+53
| | | | | | optimizing moves to use 2 byte VEX prefix. llvm-svn: 270394
* [AVX512] Add patterns to implement stores of extracts of least signficant ↵Craig Topper2016-05-221-0/+123
| | | | | | | | subvectors using XMM or YMM stores instead of the vector extract instructions. Similar is already done for AVX and we had lost it going to AVX512VL. llvm-svn: 270383
* [x86, AVX] don't add a vzeroupper if that's what the code is already doing ↵Sanjay Patel2016-05-221-0/+6
| | | | | | | | | | | | | | | (PR27823) This isn't the complete fix, but it handles the trivial examples of duplicate vzero* ops in PR27823: https://llvm.org/bugs/show_bug.cgi?id=27823 ...and amusingly, the bogus cases already exist as regression tests, so let's take this baby step. We'll need to do more in the general case where there's legitimate AVX usage in the function + there's already a vzero in the code. Differential Revision: http://reviews.llvm.org/D20477 llvm-svn: 270378
* [AVX512] Implement missing patterns for any_extend load lowering.Igor Breger2016-05-222-55/+88
| | | | | | Differential Revision: http://reviews.llvm.org/D20513 llvm-svn: 270357
* [AVX512] The AVX512 file only need subtract_subvector index 0 patterns where ↵Craig Topper2016-05-221-15/+35
| | | | | | the source is 512-bits. The 256-bit source patterns were redundant with AVX. llvm-svn: 270356
* [AVX512] Add an AddedComplexity line to the 512-bit insert_subvector undef ↵Craig Topper2016-05-221-0/+2
| | | | | | index 0 patterns. This gives them higher priority than the memory patterns. This matches AVX1/2. llvm-svn: 270355
* [AVX512] Change the AddedComplexity on some patterns to match their AVX/SSE ↵Craig Topper2016-05-221-9/+13
| | | | | | equivalents. This helps group them close together in the isel tables and enable table compression. llvm-svn: 270354
* [AVX512] Add a couple patterns to fix some cases where two vector mask ↵Craig Topper2016-05-221-0/+11
| | | | | | inversions could appear in a row. llvm-svn: 270344
* [AVX512] Remove seemingly unnecessary AddedComplexity adjustment.Craig Topper2016-05-221-2/+0
| | | | llvm-svn: 270343
* [X86] Remove unnecessary alignment check on patterns that use VEXTRACTF128 ↵Craig Topper2016-05-211-8/+8
| | | | | | for integer types when only AVX1 is supported. llvm-svn: 270335
* [AVX512] Add patterns for extracting subvectors and storing to memory.Craig Topper2016-05-212-10/+15
| | | | llvm-svn: 270334
* [AVX512] Capitalize the Z in VEXTRACTPSzmr. Lowercase z has been primarily ↵Craig Topper2016-05-211-2/+2
| | | | | | used to indicating the zero masking behavior which is not the case here. NFC llvm-svn: 270333
* [AVX512] Rename vector extract instructions so 'mr' intead of 'rm' to ↵Craig Topper2016-05-211-2/+2
| | | | | | reflect the fact that memory is the destination. llvm-svn: 270332
* [AVX512] Fix copy/paste mistake a I made in a comment.Craig Topper2016-05-211-1/+1
| | | | llvm-svn: 270331
* [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.Michael Zuckerman2016-05-214-7/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D20438 llvm-svn: 270322
* [Clang][AVX512][intrinsics] Fix vscalef intrinsics.Michael Zuckerman2016-05-215-8/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D20324 llvm-svn: 270321
* [AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable ↵Craig Topper2016-05-212-1/+9
| | | | | | AVX2 versions of vector extract when AVX512VL is enabled. llvm-svn: 270318
* [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when ↵Craig Topper2016-05-212-30/+38
| | | | | | AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones. llvm-svn: 270317
* [AVX512] Disable AVX/AVX2 VBROADCASTSS/VBROADCASTSD patterns when AVX512VL ↵Craig Topper2016-05-211-4/+4
| | | | | | is enabled. llvm-svn: 270316
* AMDGPU: Define priorities for register classesMatt Arsenault2016-05-211-11/+31
| | | | | | | | | | Allocating larger register classes first should give better allocation results (and more importantly for myself, make the lit tests more stable with respect to scheduler changes). Patch by Matthias Braun llvm-svn: 270312
* [AVX512] Disable AVX/AVX2 patterns for VPSADBW and VPMULUDQ when the ↵Craig Topper2016-05-211-4/+4
| | | | | | AVX512VL/AVX512BWI equivalents are available. llvm-svn: 270311
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