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* On x86, f32 / f64 nodes share the same registers as 128-bit vector values.Evan Cheng2010-07-262-0/+30
| | | | llvm-svn: 109450
* Add a noteAnton Korobeynikov2010-07-261-0/+21
| | | | llvm-svn: 109448
* Temporary hack to let codegen assert or generate poor code in caseBruno Cardoso Lopes2010-07-261-8/+13
| | | | | | | | | we are using AVX and no AVX version of the desired intruction is present, this is better for incremental dev (without fallbacks it's easier to spot what's missing). Not sure this is the best hack thought (we can also disable all HasSSE* predicates by dinamically marking them 'false' if AVX is present) llvm-svn: 109434
* Currently EH lowering code expects typeinfo to be global only.Anton Korobeynikov2010-07-261-2/+11
| | | | | | | | This assumption is not satisfied due to global mergeing. Workaround the issue by temporary disablinge mergeing of const globals. Also, ignore LLVM "special" globals. This fixes PR7716 llvm-svn: 109423
* ARM fastisel isn't ready.Evan Cheng2010-07-261-1/+2
| | | | llvm-svn: 109421
* Remove extraneous semicolonDouglas Gregor2010-07-251-1/+1
| | | | llvm-svn: 109373
* Unbreak CMake buildDouglas Gregor2010-07-251-0/+1
| | | | llvm-svn: 109372
* Hook in GlobalMerge passAnton Korobeynikov2010-07-246-1/+222
| | | | llvm-svn: 109359
* Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng2010-07-242-0/+21
| | | | | | | | | | | | appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. llvm-svn: 109300
* Support x86 "eiz" and "riz" pseudo index registers in the assembler.Bruno Cardoso Lopes2010-07-243-1/+25
| | | | llvm-svn: 109295
* Use the appropriate register class for an i32 when adding ARM::LR to theJim Grosbach2010-07-231-1/+1
| | | | | | | function live in set. This will give us tGPR for Thumb1 and GPR otherwise, so the copy will be spillable. rdar://8224931 llvm-svn: 109293
* Revert 109076. It is wrong and was causing regressions. Add someDale Johannesen2010-07-231-18/+48
| | | | | | | | | | comments explaining why it was wrong. 8225024. Fix the real problem in 8213383: the code that splits very large blocks when no other place to put constants can be found was not considering the case that the block contained a Thumb tablejump. llvm-svn: 109282
* - Allow target to specify when is register pressure "too high". In most cases,Evan Cheng2010-07-232-0/+24
| | | | | | | | | | | | | it's too late to start backing off aggressive latency scheduling when most of the registers are in use so the threshold should be a bit tighter. - Correctly handle live out's and extract_subreg etc. - Enable register pressure aware scheduling by default for hybrid scheduler. For ARM, this is almost always a win on # of instructions. It's runtime neutral for most of the tests. But for some kernels with high register pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by 54 and sped up by 20%. llvm-svn: 109279
* Remove trailing whitespaceBruno Cardoso Lopes2010-07-231-30/+30
| | | | llvm-svn: 109276
* Add AVX version of CLMUL instructionsBruno Cardoso Lopes2010-07-233-0/+58
| | | | llvm-svn: 109248
* fix constness warningsGabor Greif2010-07-232-2/+4
| | | | llvm-svn: 109224
* do not (implicitly) dereference iterator many times, cache it insteadGabor Greif2010-07-231-2/+3
| | | | llvm-svn: 109222
* Declare CLMUL as a subtarget featureBruno Cardoso Lopes2010-07-231-0/+2
| | | | llvm-svn: 109207
* Add x86 CLMUL (Carry-less multiplication) cpu featureBruno Cardoso Lopes2010-07-233-3/+10
| | | | llvm-svn: 109206
* Add complete assembler support for FMA3 instructions, with descriptions and ↵Bruno Cardoso Lopes2010-07-233-0/+72
| | | | | | encodings taken from the AVX manual llvm-svn: 109204
* The only supported calling convention for X86-64 usesDale Johannesen2010-07-231-1/+14
| | | | | | | | | | | | | | | SSE, so we can't return floating point values if this is disabled. Detect this error for clang. With SSE1 only, f64 is a problem; it can be done, but neither llvm-gcc nor clang has ever generated correct code for it. Since nobody noticed this I think it's OK to treat it as an error for now. This also handles SSE-sized vectors of floating point. 8207686, 8204109. llvm-svn: 109201
* Fix some AVX instructions which didnt had HasAVX prefix. And also a problem ↵Bruno Cardoso Lopes2010-07-231-6/+8
| | | | | | with PINSRW, which was totally wrong because of a typo I introduced previously llvm-svn: 109198
* eliminate the TargetInstrInfo::GetInstSizeInBytes hook. Chris Lattner2010-07-224-5/+5
| | | | | | | | ARM/PPC/MSP430-specific code (which are the only targets that implement the hook) can directly reference their target-specific instrinfo classes. llvm-svn: 109171
* Add remaining AVX instructions (most of them dealing with GR64 destinations. ↵Bruno Cardoso Lopes2010-07-221-5/+30
| | | | | | This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step llvm-svn: 109168
* remove the JIT "NeedsExactSize" feature and supporting logic.Chris Lattner2010-07-222-9/+0
| | | | llvm-svn: 109167
* switch a private implementation of GetFunctionSizeInBytes.Chris Lattner2010-07-221-1/+14
| | | | | | | | | This is probably not the best way to implement "Force LR to be spilled if the Thumb function size is > 2048." do this, it should use the branch shortening infrastructure, but I'm just preserving functionality here. llvm-svn: 109165
* X86MCInstLower now depends on AsmPrinter being around.Chris Lattner2010-07-222-32/+11
| | | | llvm-svn: 109154
* instead of migrating it to the MC instruction encoder, justChris Lattner2010-07-223-553/+100
| | | | | | | | | | | | | | rip out the implementation of X86InstrInfo::GetInstSizeInBytes. The code being ripped out just implemented a copy and hacked up version of the (old) instruction encoder, and is buggy and terrible in other ways. Since "GetInstSizeInBytes" is really only there to support the JIT's "NeedsExactSize" hook (which noone is using), just rip out the code. I will rip out the NeedsExactSize hook next. This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter llvm-svn: 109149
* ARMv4 JIT forgets to set the lr register when making a indirect function ↵Xerxes Ranby2010-07-222-1/+14
| | | | | | call. Fixes PR7608 llvm-svn: 109125
* undo 80 column trespassing I causedGabor Greif2010-07-221-1/+2
| | | | llvm-svn: 109092
* Mark an assert-only variable as used.Chandler Carruth2010-07-221-0/+1
| | | | llvm-svn: 109091
* Fix the generated file name for CMake.Chandler Carruth2010-07-221-1/+1
| | | | llvm-svn: 109090
* Attempt to fix linking issues with CMake. Please review other CMake users,Chandler Carruth2010-07-222-2/+2
| | | | | | especially on other platforms. Is there a better way to fix this. llvm-svn: 109084
* Update CMake files.Owen Anderson2010-07-221-0/+1
| | | | llvm-svn: 109081
* Custom lower the memory barrier instructions and add supportEric Christopher2010-07-225-18/+75
| | | | | | | | for lowering without sse2. Add a couple of new testcases. Fixes a few libgomp tests and latent bugs. Remove a few todos. llvm-svn: 109078
* Fix constant island pass's handling of tBR_JTr. The offset of the ↵Evan Cheng2010-07-221-2/+10
| | | | | | | | | | | | | instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into: mov pc, r1 .align 2 LJTI0_0_0: .long LBB0_14 This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one. llvm-svn: 109076
* 80-columns.Eric Christopher2010-07-221-9/+12
| | | | llvm-svn: 109070
* Make fast isel win64-aware w.r.t. call-clobbered regsNate Begeman2010-07-221-3/+14
| | | | llvm-svn: 109069
* More register pressure aware scheduling work.Evan Cheng2010-07-211-14/+11
| | | | llvm-svn: 109064
* Add more 256-bit forms for a bunch of regular AVX instructionsBruno Cardoso Lopes2010-07-212-76/+160
| | | | | | | Add 64-bit (GR64) versions of some instructions (which are not described in their SSE forms, but are described in AVX) llvm-svn: 109063
* Fixes win64. It was broken by a previous patch where I missed the !isWin64Rafael Espindola2010-07-211-4/+8
| | | | | | and then forced every register to be a vr128 on win64. llvm-svn: 109060
* For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumbJim Grosbach2010-07-211-0/+17
| | | | | | rdar://8202967 llvm-svn: 109057
* add some rough support for making mcinst lowering work without anChris Lattner2010-07-211-5/+23
| | | | | | | | asmprinter or mangler around. This is option #B for killing off X86InstrInfo::GetInstSizeInBytes. Option #A (killing "needsexactsize") was sent for consideration to llvmdev. llvm-svn: 109056
* Baby steps towards ARM fast-isel.Eric Christopher2010-07-215-1/+89
| | | | llvm-svn: 109047
* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-211-2/+1
| | | | llvm-svn: 109045
* Add missing AVX convert instructions. Those instructions are not described ↵Bruno Cardoso Lopes2010-07-211-22/+56
| | | | | | in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it llvm-svn: 109039
* Fix a couple issues with Win64 ABINate Begeman2010-07-212-6/+3
| | | | | | | | | | | 1) all registers were spilled as xmm, regardless of actual size 2) win64 abi doesn't do the varargs-size-in-%al thing Still to look into: xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't. llvm-svn: 109035
* Avoid AVX instructions to be selected instead of its SSE formBruno Cardoso Lopes2010-07-211-1/+1
| | | | llvm-svn: 109032
* Fix calling convention on ARM if vfp2+ is enabled.Rafael Espindola2010-07-211-1/+5
| | | | llvm-svn: 109009
* Pulling out previous patch, must've run the tests inEric Christopher2010-07-213-40/+3
| | | | | | the wrong directory. llvm-svn: 109005
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