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* long double 9 of N. This finishes up the X86-32 bitsDale Johannesen2007-08-091-1/+13
| | | | | | | | (constants are still not handled). Adds ConvertActions to control fp-to-fp conversions (these are currently defaulted for all other targets, so no changes there). llvm-svn: 40958
* Fix arguments for some Altivec instructions. From SWB.Dale Johannesen2007-08-091-9/+15
| | | | llvm-svn: 40957
* Fix spelling of mtvscr and mfvscr.Dale Johannesen2007-08-071-2/+2
| | | | llvm-svn: 40908
* Long double patch 8 of N: make it partially work inDale Johannesen2007-08-073-100/+100
| | | | | | | | | | | SSE mode (all but conversions <-> other FP types, I think): >>Do not mark all-80-bit operations as "Requires[FPStack]" (which really means "not SSE"). >>Refactor load-and-extend to facilitate this. >>Update comments. >>Handle long double in SSE when computing FP_REG_KILL. llvm-svn: 40906
* Initial JIT support for ARM by Raul Fernandes Herbster.Evan Cheng2007-08-079-275/+889
| | | | llvm-svn: 40887
* Long double patch 7 of N, unless I lost count:). Dale Johannesen2007-08-073-1/+37
| | | | | | | | Last x87 bits for full functionality (not thoroughly tested, and long doubles do not work in SSE modes at all - use -mcpu=i486 for now) llvm-svn: 40886
* Replace 4-line function with 10-line version per review comment.Dale Johannesen2007-08-061-4/+10
| | | | llvm-svn: 40881
* Move lengthy conditional down 1 level per review comment.Dale Johannesen2007-08-062-5/+6
| | | | llvm-svn: 40878
* Get X86 long double calling convention to workDale Johannesen2007-08-064-3/+34
| | | | | | | (on Darwin, anyway). Fix some table omissions for LD arithmetic. llvm-svn: 40877
* Make 80-bit store maintain simulated FP stack correctly.Dale Johannesen2007-08-061-1/+2
| | | | llvm-svn: 40868
* Fix minor doxygen nits.Reid Spencer2007-08-051-3/+3
| | | | llvm-svn: 40854
* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-058-6/+162
| | | | | | Lots of problems yet but some simple things work. llvm-svn: 40847
* This is the patch to provide clean intrinsic function overloading support in ↵Chandler Carruth2007-08-041-2/+2
| | | | | | | | LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported. llvm-svn: 40807
* Make x86 long double alignment 32 for everything butDale Johannesen2007-08-031-1/+3
| | | | | | Darwin (which makes size within a struct==96) llvm-svn: 40796
* long double patch 2 of N. Handle it in TargetData.Dale Johannesen2007-08-036-7/+19
| | | | | | | (I've tried to get the info right for all targets, but I'm not expert on all of them - check yours.) llvm-svn: 40792
* add an observationChris Lattner2007-08-031-0/+27
| | | | llvm-svn: 40772
* More explicit keywords.Dan Gohman2007-08-026-6/+6
| | | | llvm-svn: 40757
* Fix the alignment requirements of several unpck and shuf instructions.Dan Gohman2007-08-022-13/+21
| | | | | | | | Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's memory operand alignment can be tested as well, with a fix to avoid breaking MMX's use of isPSHUFDMask. llvm-svn: 40756
* Fix pastos in vector arithmetic intrinsics.Dan Gohman2007-08-021-4/+4
| | | | llvm-svn: 40754
* Mark the SSE and MMX load instructions thatDan Gohman2007-08-022-0/+6
| | | | | | | | | | X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle with the isReMaterializable flag so that it is given a chance to handle them. Without hoisting constant-pool loads from loops this isn't very visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from making a copy of the constant pool on the stack. llvm-svn: 40736
* Switch some multiplication instructions over to the new scheme for testing.Evan Cheng2007-08-022-12/+53
| | | | llvm-svn: 40723
* Can't handle offset and scale if rip-relative addressing is to be used.Evan Cheng2007-08-011-6/+10
| | | | llvm-svn: 40703
* Mac OS X X86-64 low 4G address not available.Evan Cheng2007-08-011-4/+4
| | | | llvm-svn: 40702
* Mac OS X X86-64 low 4G address not available.Evan Cheng2007-08-014-1/+21
| | | | llvm-svn: 40701
* Some out operands were incorrectly specified as input operands.Evan Cheng2007-08-012-17/+17
| | | | llvm-svn: 40697
* Missing Requires.Evan Cheng2007-08-011-2/+2
| | | | llvm-svn: 40691
* Be more precise.Evan Cheng2007-08-011-1/+1
| | | | llvm-svn: 40689
* Change a .size directive to use a tab instead of a space, for consistency.Dan Gohman2007-08-011-1/+1
| | | | llvm-svn: 40672
* Indexed loads each has 2 outputs.Evan Cheng2007-08-011-10/+10
| | | | llvm-svn: 40658
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-315-1117/+1117
| | | | | | | | | mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
* Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc ↵Evan Cheng2007-07-316-235/+248
| | | | | | (v4f32 s2v (f32 load ))), 0) -> (i32 load ) llvm-svn: 40628
* This isn't safe when there are uses of load's chain result.Evan Cheng2007-07-311-11/+4
| | | | llvm-svn: 40617
* Use tabs more consistently in assembler pseudo-ops.Dan Gohman2007-07-302-5/+5
| | | | llvm-svn: 40594
* Fix the comment for getClosestTargetForJIT to reflect the fact thatDan Gohman2007-07-301-4/+3
| | | | | | it does not have a Module parameter. llvm-svn: 40590
* More explicit keywords.Dan Gohman2007-07-301-1/+1
| | | | llvm-svn: 40589
* Vector fneg must be expanded into fsub -0.0, X.Evan Cheng2007-07-303-2/+21
| | | | llvm-svn: 40586
* Change the x86 backend to use extract_subreg for truncation operations. ↵Christopher Lamb2007-07-296-113/+37
| | | | | | Passes DejaGnu, SingleSource and MultiSource. llvm-svn: 40578
* Add register info needed to use subreg sets on X86.Christopher Lamb2007-07-281-2/+51
| | | | llvm-svn: 40572
* Trampoline codegen support for X86-32.Duncan Sands2007-07-275-12/+130
| | | | llvm-svn: 40566
* Re-apply 40504, but with a fix for the segfault it caused in oggenc:Dan Gohman2007-07-273-75/+42
| | | | | | | | | Make the alignedload and alignedstore patterns always require 16-byte alignment. This way when they are used in the "Fs" instructions, in which a vector instruction is used for a scalar purpose, they can still require the full vector alignment. And add a regression test for this. llvm-svn: 40555
* Support for trampolines, except for X86 codegen which isDuncan Sands2007-07-278-3/+34
| | | | | | still under discussion. llvm-svn: 40549
* Reverting 40504 for now. It's breaking oggenc.Evan Cheng2007-07-273-35/+70
| | | | llvm-svn: 40547
* Make sure epilogue esp adjustment is placed before any terminator and pop ↵Evan Cheng2007-07-261-2/+3
| | | | | | instructions. llvm-svn: 40538
* Don't pollute the meaning of isUnpredicatedTerminator.Evan Cheng2007-07-261-7/+12
| | | | llvm-svn: 40537
* Minor bug.Evan Cheng2007-07-261-3/+3
| | | | llvm-svn: 40535
* In the .loc directive, print the fields as "debug" fields, so theyDan Gohman2007-07-261-1/+1
| | | | | | don't get decorated as if for immediate fields for instructions. llvm-svn: 40529
* Fix a whitespace difference between CMPSSrr and CMPSDrr.Dan Gohman2007-07-261-2/+1
| | | | llvm-svn: 40528
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-0/+12
| | | | | | MBB's. PR1350 llvm-svn: 40518
* Same goes for constantpool, etc.Evan Cheng2007-07-261-5/+5
| | | | llvm-svn: 40517
* Add selection DAG nodes for subreg insert/extract. PR1350Christopher Lamb2007-07-261-0/+5
| | | | llvm-svn: 40516
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