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* Random #include pruning.Benjamin Kramer2009-10-201-1/+2
| | | | llvm-svn: 84632
* This file is replaeced by PIC16Section.h.Sanjiv Gupta2009-10-201-88/+0
| | | | llvm-svn: 84628
* implement some more easy hooks.Chris Lattner2009-10-202-3/+34
| | | | llvm-svn: 84614
* Implement some hooks, make printOperand abort if unknown modifiers areChris Lattner2009-10-202-9/+129
| | | | | | present. llvm-svn: 84613
* t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.Chris Lattner2009-10-201-2/+2
| | | | llvm-svn: 84611
* Wire up the ARM MCInst printer, for llvm-mc.Daniel Dunbar2009-10-202-8/+33
| | | | llvm-svn: 84600
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-202-15/+0
| | | | | | functions are not needed. llvm-svn: 84587
* Enable post-pass frame index register scavenging for ARM and Thumb2Jim Grosbach2009-10-202-20/+10
| | | | llvm-svn: 84585
* lower ARM::MOVi32imm properly.Chris Lattner2009-10-201-2/+36
| | | | llvm-svn: 84583
* add support for external symbols. The mc instprinter can now handleChris Lattner2009-10-202-3/+17
| | | | | | | reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing identical output except for superior formatting of constant pool entries. llvm-svn: 84582
* get fancy: support basic block operands. Yay for jumps.Chris Lattner2009-10-203-15/+12
| | | | llvm-svn: 84579
* add supprort for the 'sbit' operand, MOVi apparently has one.Chris Lattner2009-10-203-1/+11
| | | | llvm-svn: 84577
* add support for instruction predicates.Chris Lattner2009-10-202-3/+8
| | | | llvm-svn: 84575
* implement printSORegOperand, add lowering for the nasty and despicable ↵Chris Lattner2009-10-204-5/+75
| | | | | | MOVi2pieces :) llvm-svn: 84573
* Refs: A8-598.Jim Grosbach2009-10-202-10/+24
| | | | | | | | | Leave Inst{11-8}, which represents the starting byte index of the extracted result in the concatenation of the operands and is left unspecified. Patch by Johnny Chen. llvm-svn: 84572
* Add missing encoding bits to NLdSt class of instructions.Jim Grosbach2009-10-201-0/+4
| | | | | | Patch by Johnny Chen. llvm-svn: 84570
* X86 should ignore implicit regs when lowering to MCInst also,Chris Lattner2009-10-191-0/+2
| | | | | | no functionality change. llvm-svn: 84567
* handle addmode4 modifiers, fix a fixme in printRegisterListChris Lattner2009-10-192-10/+4
| | | | | | by ignoring all implicit regs when lowering. llvm-svn: 84566
* simplify by using the twine form of GetOrCreateSymbolChris Lattner2009-10-191-8/+5
| | | | llvm-svn: 84565
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-194-17/+3
| | | | llvm-svn: 84563
* use EmitLabel instead of text emissionChris Lattner2009-10-191-4/+6
| | | | llvm-svn: 84562
* add a twine version of MCContext::GetOrCreateSymbol.Chris Lattner2009-10-192-6/+7
| | | | llvm-svn: 84561
* lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entriesChris Lattner2009-10-193-6/+32
| | | | | | | | | | | | | like: @ BB#1: .align 2 LCPI1_0: .long L_.str-(LPC0+8) Note that proper indentation of the label :) llvm-svn: 84558
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-192-19/+33
| | | | | | | | | | appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. llvm-svn: 84554
* add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.Chris Lattner2009-10-193-5/+34
| | | | llvm-svn: 84553
* add register list and hacked up addrmode #4 support, we now get this:Chris Lattner2009-10-192-2/+48
| | | | | | | | | | | | | | | | | | _main: stmsp! sp!, {r7, lr} mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, [sp] ldr r0, LCPI1_0 bl _printf ldr r0, [sp] mov sp, r7 ldmsp! sp!, {r7, pc} Note the unhappy ldm/stm because of modifiers being ignored. llvm-svn: 84546
* revert r84540, fixing build breakage I didn't see because ofChris Lattner2009-10-192-7/+7
| | | | | | broken makefile deps :( llvm-svn: 84544
* add addrmode2 support, getting us up to:Chris Lattner2009-10-192-1/+35
| | | | | | | | | | | | | | | | _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, [sp] ldr r0, LCPI1_0 bl _printf ldr r0, [sp] mov sp, r7 ldm , llvm-svn: 84543
* add jump tables, constant pools and some trivial globalChris Lattner2009-10-194-22/+94
| | | | | | | | | | | | | | | | | | | | lowering stuff. We can now compile hello world to: _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, ldr r0, bl _printf ldr r0, mov sp, r7 ldm , Almost looks like arm code :) llvm-svn: 84542
* pass mangler in as a reference instead of a pointer.Chris Lattner2009-10-192-7/+7
| | | | llvm-svn: 84540
* reduce #includesChris Lattner2009-10-191-4/+3
| | | | llvm-svn: 84536
* add printing support for SOImm operands, getting us to:Chris Lattner2009-10-193-4/+40
| | | | | | | | | | | _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, llvm-svn: 84535
* wire up some basic printOperand goodness, giving us stuff like this beforeChris Lattner2009-10-193-20/+34
| | | | | | | | | | | | | we abort: _main: stm , mov r7, sp sub sp, sp, mov r0, str r0, llvm-svn: 84532
* add the files that go with the previous revChris Lattner2009-10-192-0/+135
| | | | llvm-svn: 84531
* wire up skeletal support for having llc print instructionsChris Lattner2009-10-192-11/+58
| | | | | | | | through mcinst lowering -> mcinstprinter, when llc is passed the -enable-arm-mcinst-printer flag. Currently this is very "aborty". llvm-svn: 84530
* wire up ARM's printMCInst method. Now llvm-mc should be able to produce Chris Lattner2009-10-191-0/+5
| | | | | | | "something" when printing MCInsts, it will just be missing all the operand info. llvm-svn: 84528
* stub out a minimal ARMInstPrinter.Chris Lattner2009-10-193-1/+121
| | | | llvm-svn: 84527
* remove strings from instructions who are never asmprinted.Chris Lattner2009-10-194-30/+15
| | | | | | | | | All of these "subreg32" modifier instructions are handled explicitly by the MCInst lowering phase. If they got to the asmprinter, they would explode. They should eventually be replace with correct use of subregs. llvm-svn: 84526
* simplify code, reducing string thrashing.Chris Lattner2009-10-191-20/+10
| | | | llvm-svn: 84521
* switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.Chris Lattner2009-10-191-14/+21
| | | | llvm-svn: 84520
* use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.Chris Lattner2009-10-191-14/+23
| | | | llvm-svn: 84519
* remove dead mapChris Lattner2009-10-191-7/+0
| | | | llvm-svn: 84513
* don't bother trying to avoid emitting redundant constant pool alignment ↵Chris Lattner2009-10-191-16/+3
| | | | | | directives. llvm-svn: 84512
* remove accidental comment.Chris Lattner2009-10-191-2/+0
| | | | llvm-svn: 84510
* emit .subsections_via_symbols through MCStreamer instead of textually.Chris Lattner2009-10-193-3/+5
| | | | llvm-svn: 84509
* cleanup doFinalization -> EmitEndOfAsmFile.Chris Lattner2009-10-191-6/+3
| | | | llvm-svn: 84508
* PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 ↵Nate Begeman2009-10-191-2/+2
| | | | | | instructions. llvm-svn: 84506
* Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS.Torok Edwin2009-10-191-1/+2
| | | | | | | LLC was scheduling compares before the adds causing wrong branches to be taken in programs, resulting in misoptimized code wherever atomic adds where used. llvm-svn: 84485
* Add support for matching shuffle patterns with palignr.Nate Begeman2009-10-193-12/+116
| | | | llvm-svn: 84459
* Turn on post-alloc scheduling for x86.Evan Cheng2009-10-181-2/+1
| | | | llvm-svn: 84431
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