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* X86: Rename the CLMUL target feature to PCLMUL.Benjamin Kramer2012-05-316-25/+25
| | | | | | | It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. llvm-svn: 157745
* Added FMA3 Intel instructions.Elena Demikhovsky2012-05-316-49/+409
| | | | | | | | I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks. I added tests for GodeGen and intrinsics. I did not change llvm.fma.f32/64 - it may be done later. llvm-svn: 157737
* Add intrinsic for pclmulqdq instruction.Craig Topper2012-05-311-15/+13
| | | | llvm-svn: 157731
* Cleanup and factoring of mips16 tablegen classes. Make register classesAkira Hatanaka2012-05-313-61/+89
| | | | | | | | | CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16 jalr instruction. Patch by Reed Kotler. llvm-svn: 157730
* Avoid depending on list orders and register numbering.Jakob Stoklund Olesen2012-05-301-6/+9
| | | | | | This code is covered by test/CodeGen/ARM/arm-modifier.ll. llvm-svn: 157720
* Extract some pointer hacking to a function.Jakob Stoklund Olesen2012-05-301-22/+22
| | | | | | Switch to MCSuperRegIterator while we're there. llvm-svn: 157717
* Add support for the mips inline asm 'm' output modifier.Eric Christopher2012-05-301-0/+5
| | | | | | Patch by Jack Carter. llvm-svn: 157709
* Fix some uses of getSubRegisters() to use getSubReg() instead.Jakob Stoklund Olesen2012-05-303-10/+13
| | | | | | | It is better to address sub-registers directly by name instead of relying on their position in the sub-register list. llvm-svn: 157703
* it's pointed out that R11 can be used for magic things, and doing things ↵Chris Lattner2012-05-301-1/+1
| | | | | | just for 64-bit registers is silly. Just optimize 3 more. llvm-svn: 157699
* Extend the (abi-irrelevant) return convention to be able to return more than ↵Chris Lattner2012-05-301-4/+7
| | | | | | | | | | | | two values in integer registers. This is already supported by the fastcc convention, but it doesn't hurt to support it in the standard conventions as well. In cases where we can cheat at the calling convention, this allows us to avoid returning things through memory in more cases. llvm-svn: 157698
* [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.Chad Rosier2012-05-301-0/+36
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157696
* Port support for SSE4a extrq/insertq to the old jit code emitter.Benjamin Kramer2012-05-301-1/+1
| | | | llvm-svn: 157685
* Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer2012-05-292-2/+28
| | | | | | | | | | | extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
* Update CPPBackend to new API for AttrListPtr::get.Nicolas Geoffray2012-05-291-1/+1
| | | | llvm-svn: 157624
* ConstantRangesSet renamed to IntegersSubset. CRSBuilder renamed to ↵Stepan Dyatkovskiy2012-05-291-1/+1
| | | | | | IntegersSubsetMapping. llvm-svn: 157612
* Fix predicate HasStandardEncoding in MipsInstrInfo.td per suggestion ofAkira Hatanaka2012-05-251-3/+2
| | | | | | Benjamin Kramer. llvm-svn: 157504
* Delete MipsExpandPseudo.cpp.Akira Hatanaka2012-05-251-117/+0
| | | | llvm-svn: 157496
* Move the code in MipsExpandPseudo to MipsInstrInfo::expandPostRAPseudo.Akira Hatanaka2012-05-255-9/+53
| | | | | | Delete MipsExpandPseudo. llvm-svn: 157495
* Remove the code that expands MIPS' .cpload directive.Akira Hatanaka2012-05-252-24/+0
| | | | llvm-svn: 157494
* Remove the code that emits MIPS' .cprestore directive.Akira Hatanaka2012-05-253-50/+0
| | | | llvm-svn: 157493
* Remove pseudo instructions that are no longer used.Akira Hatanaka2012-05-252-29/+0
| | | | llvm-svn: 157492
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-2524-190/+184
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Simplify code for calling a function where CanLowerReturn fails, fixing a ↵Eli Friedman2012-05-251-2/+1
| | | | | | small bug in the process. llvm-svn: 157446
* Shrink.Jakob Stoklund Olesen2012-05-241-7145/+18
| | | | llvm-svn: 157433
* Remove the PTX back-end and all of its artifacts (triple, etc.)Justin Holewinski2012-05-2454-6749/+1
| | | | | | | | This back-end was deprecated in favor of the NVPTX back-end. NV_CONTRIB llvm-svn: 157417
* Turn on mips16 pseudo op when compiling for mips16.Akira Hatanaka2012-05-241-1/+7
| | | | | | | | Expand test case for this. Patch by Reed Kotler. llvm-svn: 157410
* Enable Mips16 compiler to compile a null program.Akira Hatanaka2012-05-244-6/+29
| | | | | | | | First code from the Mips16 compiler. Includes trivial test program. Patch by Reed Kotler. llvm-svn: 157408
* Convert assert(0) to llvm_unreachable.Craig Topper2012-05-245-31/+20
| | | | llvm-svn: 157380
* Use uint16_t to store registers in static tables. Matches other tables.Craig Topper2012-05-241-5/+5
| | | | llvm-svn: 157375
* Use uint16_t to store register number in static tables to match other tables.Craig Topper2012-05-241-7/+7
| | | | llvm-svn: 157374
* Make some opcode tables static and const. Allows code to avoid making copies ↵Craig Topper2012-05-241-173/+219
| | | | | | to pass the tables around. llvm-svn: 157373
* Mark a couple arrays as static and const. Use array_lengthof instead of ↵Craig Topper2012-05-242-6/+6
| | | | | | sizeof/sizeof. llvm-svn: 157369
* Mark a static array as const.Craig Topper2012-05-241-1/+1
| | | | llvm-svn: 157368
* Mark a static table as const. Shrink opcode size in static tables to ↵Craig Topper2012-05-241-14/+9
| | | | | | uint16_t. Simplify loop iterating over one of those tables. No functional change intended. llvm-svn: 157367
* Tidy up naming for consistency and other cleanup. No functional change ↵Chad Rosier2012-05-231-10/+9
| | | | | | intended. llvm-svn: 157358
* [arm-fast-isel] Add support for non-global callee.Chad Rosier2012-05-231-7/+17
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157336
* Tidy up spacing.Craig Topper2012-05-231-2/+2
| | | | llvm-svn: 157313
* Fix indentation of wrapped line for readability. No functional change.Craig Topper2012-05-231-1/+1
| | | | llvm-svn: 157309
* ARMDisassembler.cpp: Fix utf8 char in comments.NAKAMURA Takumi2012-05-221-3/+3
| | | | llvm-svn: 157292
* Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug ↵Craig Topper2012-05-221-1/+1
| | | | | | introduced in r157043. Fixes PR12908. llvm-svn: 157236
* This patch adds a predicate to existing mips32 and mips64 so that thoseAkira Hatanaka2012-05-226-101/+134
| | | | | | | | | | | | | | | | | | | instruction encodings can be excluded during mips16 processing. This revision fixes the issue raised by Jim Grosbach. bool hasStandardEncoding() const { return !inMips16Mode(); } When micromips is added it will be bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); } No additional testing is needed other than to assure that there is no regression from this patch. Patch by Reed Kotler. llvm-svn: 157234
* ARM: .end_data_region mismatch in Thumb2.Jim Grosbach2012-05-211-2/+5
| | | | | | | | | | 32-bit offset jump tables just use real branch instructions and so aren't marked as data regions. We were still emitting the .end_data_region marker though, which assert()ed. rdar://11499158 llvm-svn: 157221
* Thumb2: RSB source register should be rGRP not GPRnopc.Jim Grosbach2012-05-211-4/+4
| | | | | | t2RSB defined the operand correctly, but tRSBS didn't. llvm-svn: 157200
* Allow 256-bit shuffles to still be split even if only half of the shuffle ↵Craig Topper2012-05-211-15/+44
| | | | | | comes from two 128-bit pieces. llvm-svn: 157175
* Make the global base reg GR32_NOSP.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | It can sometimes be used in addressing modes that don't support %ESP. llvm-svn: 157165
* Add a missing PPC 64-bit stwu pattern.Hal Finkel2012-05-201-0/+8
| | | | | | | This seems to fix the remaining compile-time failures on PPC64 when compiling with -enable-ppc-preinc. llvm-svn: 157159
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | llvm-svn: 157152
* Transfer memory operands to the right instruction.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | They need to go on the PICLDR as the verifier points out. llvm-svn: 157151
* Add a FIXME about access to negative stack-pointer offsets on PPC32.Hal Finkel2012-05-191-0/+2
| | | | | | | | | | | | | | The current code will generate a prologue which starts with something like: mflr 0 stw 31, -4(1) stw 0, 4(1) stwu 1, -16(1) But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed. This was pointed out by Peter Bergner. llvm-svn: 157133
* On Haswell, perfer storing YMM registers using a single instruction.Nadav Rotem2012-05-191-5/+4
| | | | llvm-svn: 157129
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