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* R600/SI: remove some more unused codeChristian Konig2013-02-162-52/+0
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175350
* R600/structurizer: improve inverting conditionsChristian Konig2013-02-161-1/+39
| | | | | | | | | | Stop adding more instructions than necessary. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175349
* R600/structurizer: improve loop handlingChristian Konig2013-02-161-196/+148
| | | | | | | | | | Generate more than one loop if it seems to make sense. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175348
* R600/structurizer: improve finding condition valuesChristian Konig2013-02-161-9/+22
| | | | | | | | | | Using the new NearestCommonDominator class. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175347
* R600/structurizer: improve PHI value findingChristian Konig2013-02-161-0/+6
| | | | | | | | | | Using the new NearestCommonDominator class. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175346
* R600/structurizer: add class to find the Nearest Common DominatorChristian Konig2013-02-161-0/+66
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175345
* Use a different scheme to chose 16/32 variants. This scheme is moreReed Kotler2013-02-162-11/+7
| | | | | | | consistent with how BuildMI works. No new tests needed. All should work the same as before. llvm-svn: 175342
* Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling2013-02-164-73/+89
| | | | | | new features. llvm-svn: 175336
* [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier2013-02-161-1/+1
| | | | | | | | | | | If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 llvm-svn: 175334
* [mips] Remove SDNPWantParent from the list of SDNodeProperties.Akira Hatanaka2013-02-162-17/+14
| | | | | | No functionality change intended. llvm-svn: 175325
* Temporary revert of 175320.Bill Wendling2013-02-154-90/+74
| | | | llvm-svn: 175322
* Reinitialize the ivars in the subtarget.Bill Wendling2013-02-154-74/+90
| | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. llvm-svn: 175320
* Support changing the subtarget features in ARM.Bill Wendling2013-02-152-4/+29
| | | | llvm-svn: 175315
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-152-41/+67
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
* [ms-inline asm] Adjust the EndLoc to account for the ']'.Chad Rosier2013-02-151-1/+2
| | | | llvm-svn: 175312
* [mips] Clean up class MipsCCInfo.Akira Hatanaka2013-02-152-58/+74
| | | | | | No functionality change intended. llvm-svn: 175310
* [mips] Split SelectAddr, which was used to match address patterns, into twoAkira Hatanaka2013-02-153-18/+71
| | | | | | | | | | | functions. Set AddedComplexity to determine the order in which patterns are matched. This simplifies selection of floating point loads/stores. No functionality change intended. llvm-svn: 175300
* Remove a final dependency on the form field in tablegen; which is a remnantReed Kotler2013-02-152-6/+10
| | | | | | | of the old jit and which we don't intend to support in mips16 or micromips. This dependency is for the testing of whether an instruction is a pseudo. llvm-svn: 175297
* Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma2013-02-151-33/+25
| | | | | | | | support constant extension. This patch doesn't introduce any functionality changes. llvm-svn: 175280
* AArch64: add branch fixup pass.Tim Northover2013-02-156-0/+652
| | | | | | | | | | | | | This is essentially a stripped-down version of the ConstandIslands pass (which always had these two functions), providing just the features necessary for correctness. In particular there needs to be a way to resolve the situation where a conditional branch's destination block ends up out of range. This issue crops up when self-hosting for AArch64. llvm-svn: 175269
* Give these callbacks hidden visibility. It is better to not export them moreRafael Espindola2013-02-152-4/+6
| | | | | | | than we need to and some ELF linkers complain about directly accessing symbols with default visibility. llvm-svn: 175268
* Don't make assumptions about the mangling of static functions in extern "C"Rafael Espindola2013-02-152-27/+17
| | | | | | | | blocks. We still don't have consensus if we should try to change clang or the standard, but llvm should work with compilers that implement the current standard and mangle those functions. llvm-svn: 175267
* Make helpers static. Add missing include so LLVMInitializeObjCARCOpts gets C ↵Benjamin Kramer2013-02-151-1/+1
| | | | | | linkage. llvm-svn: 175264
* AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover2013-02-1512-1610/+83
| | | | | | | | This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. llvm-svn: 175258
* AArch64: refactor frame handling to use movz/movk for overlarge offsets.Tim Northover2013-02-151-12/+29
| | | | | | | | In the near future litpools will be in a different section, which means that any access to them is at least two instructions. This makes the case for a movz/movk pair (if total offset <= 32-bits) even more compelling. llvm-svn: 175257
* Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler2013-02-151-7/+10
| | | | | | | not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. llvm-svn: 175237
* [mips] Disallow moving load/store instructions past volatile instructions.Akira Hatanaka2013-02-141-1/+1
| | | | | | | Unfortunately, I wasn't able to create a test case that demonstrates the problem I was trying to fix with this patch. llvm-svn: 175226
* [mips] Replace usage of SmallSet with BitVector, which is used to keep track ofAkira Hatanaka2013-02-141-86/+83
| | | | | | | defined and used registers. Also add a few helper functions to simplify the code. llvm-svn: 175224
* [mips] Fix comments and coding style violations. Declare functions to be const.Akira Hatanaka2013-02-141-64/+47
| | | | llvm-svn: 175222
* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-141-0/+5
| | | | | | | | | | | | | | assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions llvm-svn: 175221
* The operand listing is very much outdated.Eli Bendersky2013-02-141-5/+2
| | | | llvm-svn: 175220
* [mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka2013-02-141-38/+29
| | | | | | | | 1. Define and use function terminateSearch. 2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator. 3. Delete the line which checks whether an instruction is a pseudo. llvm-svn: 175219
* Simplify code. Remove "else after return".Jakub Staszak2013-02-141-5/+4
| | | | llvm-svn: 175212
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-145-259/+252
| | | | | | | | This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. llvm-svn: 175205
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-145-0/+54
| | | | | | -feature flag, instructions definitions, test cases llvm-svn: 175196
* R600/SI: Fix int_SI_fs_interp_constantMichel Danzer2013-02-145-37/+34
| | | | | | | | | | | | | | | | The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175193
* 80-colNadav Rotem2013-02-141-1/+2
| | | | llvm-svn: 175189
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
| | | | | | This patch doesn't introduce any functionality changes. llvm-svn: 175187
* Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao2013-02-142-6/+150
| | | | | | | | inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi llvm-svn: 175186
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-142-1/+3
| | | | | | | | | It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175183
* R600: Export instructions are no longer terminatorVincent Lejeune2013-02-141-2/+2
| | | | | | | | This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175182
* R600: Fold zero/one in export instructionsVincent Lejeune2013-02-143-80/+55
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175181
* R600: Do not fold modifier/litterals in vector instVincent Lejeune2013-02-141-2/+5
| | | | | | | | | This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175180
* AArch64: switch from neverHasSideEffects to hasSideEffects.Tim Northover2013-02-141-4/+4
| | | | llvm-svn: 175176
* AArch64: stop claiming that NEON registers are usable for now.Tim Northover2013-02-141-11/+0
| | | | | | | | | | If vector types have legal register classes, then LLVM bypasses LegalizeTypes on them, which causes faults currently since the code to handle them isn't in place. This fixes test failures when AArch64 is the default target. llvm-svn: 175172
* AArch64: add block comments where missingTim Northover2013-02-1419-11/+86
| | | | | | Only comments affected. No code change at all. llvm-svn: 175169
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-141-4/+8
| | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-141-3/+17
| | | | | | Added a test. llvm-svn: 175144
* R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer2013-02-141-1/+1
| | | | | | | Fixes assertion failure in newly added lit test. Might just be a bandaid that needs to be revisited. llvm-svn: 175139
* Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola2013-02-142-1/+7
| | | | llvm-svn: 175133
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