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* Refactor more duplicated code.Rafael Espindola2016-06-162-21/+18
| | | | llvm-svn: 272939
* NFC; refactor getFrameIndexReferenceFromSPSanjoy Das2016-06-162-17/+14
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: ... into getFrameIndexReferencePreferSP. This change folds the fail-then-retry logic into getFrameIndexReferencePreferSP. There is a non-functional but behaviorial change in WinException -- earlier if `getFrameIndexReferenceFromSP` failed we'd trip an assert, but now we'll silently use the (wrong) offset from the base pointer. I could not write the assert I'd like to write ("FrameReg == StackRegister", like I've done in X86FrameLowering) since there is no easy way to get to the stack register from WinException (happy to be proven wrong here). One solution to this is to add a `bool OnlyStackPointer` parameter to `getFrameIndexReferenceFromSP` that asserts if it could not satisfy its promise of returning an offset from a stack pointer, but that seems overkill. Reviewers: rnk Subscribers: sanjoy, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D21427 llvm-svn: 272938
* Refactor duplicated code.Rafael Espindola2016-06-161-4/+4
| | | | llvm-svn: 272936
* [x86] autoupgrade and remove AVX2 integer min/max intrinsicsSanjay Patel2016-06-161-12/+0
| | | | | | | This will (hopefully very temporarily) break clang. The clang side of this should be the next commit. llvm-svn: 272932
* AMDGPU: Add v_mad 16-bit instructions definition.Wei Ding2016-06-162-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D21362 llvm-svn: 272919
* Don't print (PLT) on arm.Rafael Espindola2016-06-165-32/+4
| | | | | | | | | The R_ARM_PLT32 relocation is deprecated and is not produced by MC. This means that the code being deleted is dead from the .o point of view and was making the .s more confusing. llvm-svn: 272909
* [x86] autoupgrade and remove SSE2/SSE41 integer min/max intrinsicsSanjay Patel2016-06-161-12/+0
| | | | | | | | Follow-up to: http://reviews.llvm.org/rL272806 http://reviews.llvm.org/rL272807 llvm-svn: 272907
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-3/+1
| | | | llvm-svn: 272905
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-6/+5
| | | | llvm-svn: 272904
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-4/+5
| | | | llvm-svn: 272903
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-3/+5
| | | | llvm-svn: 272901
* [mips] Fix small typo. NFC.Vasileios Kalintiris2016-06-161-1/+1
| | | | llvm-svn: 272895
* [mips][mips16] Fix machine verifier errors about incorrect register classes ↵Daniel Sanders2016-06-167-161/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on load/stores. Summary: [ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore lower frameindex nodes such that there is a copy to a CPU16Regs register. This is now done consistently using a separate addressing mode that does not permit frameindex nodes. As part of this I've had to remove an optimization that reduced the number of instructions needed to work around the lack of sp-relative addresses on [ls][bh] and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as a copy of the stack pointer and it's implementation was the root cause of many of the register vs register class mismatches. lw/sw can use sp-relative addresses but we ought to ensure that we use the correct version of lw/sw internally for things like IAS. This is not currently the case and this change does not fix this. However, this change does clean it up sufficiently well to fix the machine verifier failures. Also removed irrelevant functions from stchar.ll. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21062 llvm-svn: 272882
* [llvm-objdump] Support detection of feature bits from the object and ↵Daniel Sanders2016-06-161-2/+3
| | | | | | | | | | | | | | | | | | | | implement this for Mips. Summary: The Mips implementation only covers the feature bits described by the ELF e_flags so far. Mips stores additional feature bits such as MSA in the .MIPS.abiflags section. Also fixed a small bug this revealed where microMIPS wouldn't add the EF_MIPS_MICROMIPS flag when using -filetype=obj. Reviewers: echristo, rafael Subscribers: rafael, mehdi_amini, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21125 llvm-svn: 272880
* [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructionsHrvoje Varga2016-06-165-86/+134
| | | | | | Differential Revision: http://reviews.llvm.org/D16917 llvm-svn: 272876
* [X86] Pre-size some SmallVectors using the constructor in the shuffle ↵Craig Topper2016-06-161-18/+13
| | | | | | lowering code instead of using push_back. Some of these already did this but used resize or assign instead of the constructor. NFC llvm-svn: 272872
* [X86] Remove else after return. NFCCraig Topper2016-06-161-3/+2
| | | | llvm-svn: 272871
* [X86] Inline a couple lambdas into their callers since they are only used ↵Craig Topper2016-06-161-6/+2
| | | | | | once and it all fits on a single line. NFC llvm-svn: 272869
* AArch64: allow MOV (imm) alias to be printedTim Northover2016-06-163-18/+93
| | | | | | | | | The backend has been around for years, it's pretty ridiculous that we can't even use the preferred form for printing "MOV" aliases. Unfortunately, TableGen can't handle the complex predicates when printing so it's a bunch of nasty C++. Oh well. llvm-svn: 272865
* Tidy the asm parser: 80-col, whitespace.Eric Christopher2016-06-161-8/+14
| | | | llvm-svn: 272861
* [Hexagon] Fix/simplify some conditional statementsKrzysztof Parzyszek2016-06-151-3/+3
| | | | | | Fix for PR28138. llvm-svn: 272836
* [X86]: Fix for uninitialized access introduced in r272797.Kevin B. Smith2016-06-151-0/+4
| | | | llvm-svn: 272835
* AArch64: stop trying to use 32-bit MOVZs when expanding patchpoints.Tim Northover2016-06-151-3/+3
| | | | | | | | | | | Of course the assembly was right but because the opcode was MOVZWi it was encoded as "movz w16, #65535, lsl #32" which is an unallocated encoding and would go horribly wrong on a CPU. No idea how this bug survived this long. It seems nobody is using that aspect of patchpoints. llvm-svn: 272831
* [x86] add folds for x86 vector compare nodes (PR27924)Sanjay Patel2016-06-151-0/+18
| | | | | | | | | | | | | Ideally, we can get rid of most x86 LLVM intrinsics by transforming them to IR (and some of that happened with http://reviews.llvm.org/rL272807), but it doesn't cost much to have some simple folds in the backend too while we're working on that and as a backstop. This fixes: https://llvm.org/bugs/show_bug.cgi?id=27924 Differential Revision: http://reviews.llvm.org/D21356 llvm-svn: 272828
* [X86]: Updated r272801 to promote 16 bit compares with immediate operandKevin B. Smith2016-06-151-0/+31
| | | | | | to 32 bits. This is in response to a comment by Eli Friedman. llvm-svn: 272814
* Test commit after access grant. Modified comment by adding a period. Pankaj Gode2016-06-151-1/+1
| | | | llvm-svn: 272808
* [x86] fix function name; NFCSanjay Patel2016-06-151-2/+2
| | | | llvm-svn: 272805
* [X86]: Quit promoting 8 and 16 bit compares to 32 bit.Kevin B. Smith2016-06-151-32/+0
| | | | | | Differential Revision: http://reviews.llvm.org/D21144 llvm-svn: 272801
* Revert "Preserve DebugInfo when replacing values in DAGCombiner"Nirav Dave2016-06-152-2/+4
| | | | | | | | | Reverting due to assertion failure in lib/CodeGen/SelectionDAG/InstrEmitter.cpp This reverts commit r272792. llvm-svn: 272799
* [X86]: Improve Liveness checking for X86FixupBWInsts.cppKevin B. Smith2016-06-151-39/+97
| | | | | | Differential Revision: http://reviews.llvm.org/D21085 llvm-svn: 272797
* [mips] Eliminate unused code for addrRegReg complex pattern. NFC.Vasileios Kalintiris2016-06-155-29/+0
| | | | | | | | | | Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21381 llvm-svn: 272794
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-152-4/+2
| | | | | | | | | | | | | | | | | | | [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 272792
* Reverting r272778 because there's an assertionRanjeet Singh2016-06-153-64/+13
| | | | | | failure when running the test CodeGen/ARM/intrinsics-coprocessor.ll llvm-svn: 272791
* [AMDGPU] Fix few coding style issues. NFC.Valery Pykhtin2016-06-152-23/+23
| | | | llvm-svn: 272785
* [ARM] Add support for mrrc/mrrc2 intrinsics.Ranjeet Singh2016-06-153-13/+64
| | | | | | Differential Revision: http://reviews.llvm.org/D21178 llvm-svn: 272778
* [mips] Replace AdditionalRequires<[IsGP64bit]> with GPR_64. NFC.Daniel Sanders2016-06-151-8/+4
| | | | | | | | | | | | Summary: Also fixed one case where HasMips64 was being used instead of IsGP64bit. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21028 llvm-svn: 272771
* [mips] clang-format Mips16ISelDAGToDAG.{cpp,h}Daniel Sanders2016-06-152-52/+52
| | | | llvm-svn: 272768
* [mips][msa] Fix register/register-class mismatches in emitINSERT_DF_VIDX().Daniel Sanders2016-06-151-3/+6
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21068 llvm-svn: 272765
* [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and ↵Zlatko Buljan2016-06-154-132/+197
| | | | | | | | NOR instructions Differential Revision: http://reviews.llvm.org/D16719 llvm-svn: 272764
* [AVX512] Fix BLENDM lowering patterns. Operands should be swapped to match ↵Igor Breger2016-06-151-6/+9
| | | | | | | | | | SELECT behavior. Use BLENDM instead of masked move instruction. Differential Revision: http://reviews.llvm.org/D21001 llvm-svn: 272763
* Push a dependent computation into the assert that uses it; NFCSanjoy Das2016-06-151-5/+3
| | | | | | | | | ... instead of explicitly conditioning on NDEBUG. Also use an easier to read conditional expression. (Addresses post-commit review from David Blaikie.) llvm-svn: 272762
* AMDGPU: Fix MUBUF offset bugs affecting llvm.amdgcn.buffer.* intrinsicsNicolai Haehnle2016-06-151-13/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes two related bugs. First, the generic optimization passes unfortunately generate negative constant offsets but the hardware treats SOffset as an unsigned value. Second, there is a hardware bug on SI and CI, where address clamping in MUBUF instructions does not work correctly when SOffset is larger than the buffer size. This patch works around this bug by never using SOffset. An alternative workaround would be to do the clamping manually when SOffset is too large, but generating the required code sequence during instruction selection would be rather involved, and in any case the resulting code would probably be worse. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96360 Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21326 llvm-svn: 272761
* Fix unused variable warning; NFCSanjoy Das2016-06-151-0/+2
| | | | | | | TailCallReturnAddrDelta is used only in an assert, so put it under defined(NDEBUG). llvm-svn: 272760
* Don't force SP-relative addressing for statepointsSanjoy Das2016-06-152-51/+57
| | | | | | | | | | | | | | | | | | | Summary: ... when the offset is not statically known. Prioritize addresses relative to the stack pointer in the stackmap, but fallback gracefully to other modes of addressing if the offset to the stack pointer is not a known constant. Patch by Oscar Blumberg! Reviewers: sanjoy Subscribers: llvm-commits, majnemer, rnk, sanjoy, thanm Differential Revision: http://reviews.llvm.org/D21259 llvm-svn: 272756
* AMDGPU/SI: Correctly encode constant expressionsTom Stellard2016-06-151-9/+23
| | | | | | | | | | | | | | | Summary: We we have an MCConstantExpr, we can encode it directly into the instruction instead of emitting fixups. Reviewers: artem.tamazov, vpykhtin, SamWot, nhaustov, arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21236 Change-Id: I88b3edf288d48e65c5d705fc4850d281f8e36948 llvm-svn: 272750
* AMDGPU/AsmParser: Add support for parsing symbol operandsTom Stellard2016-06-151-2/+46
| | | | | | | | | | | | | | Summary: We can now reference symbols directly in operands, like this: s_mov_b32 s0, global Reviewers: artem.tamazov, vpykhtin, SamWot, nhaustov Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21038 llvm-svn: 272748
* Remove the ScalarReplAggregates passDavid Majnemer2016-06-152-2/+2
| | | | | | | | | | Nearly all the changes to this pass have been done while maintaining and updating other parts of LLVM. LLVM has had another pass, SROA, which has superseded ScalarReplAggregates for quite some time. Differential Revision: http://reviews.llvm.org/D21316 llvm-svn: 272737
* AMDGPU: Run pointer optimization passesMatt Arsenault2016-06-151-7/+46
| | | | llvm-svn: 272736
* IR: Introduce local_unnamed_addr attribute.Peter Collingbourne2016-06-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a local_unnamed_addr attribute is attached to a global, the address is known to be insignificant within the module. It is distinct from the existing unnamed_addr attribute in that it only describes a local property of the module rather than a global property of the symbol. This attribute is intended to be used by the code generator and LTO to allow the linker to decide whether the global needs to be in the symbol table. It is possible to exclude a global from the symbol table if three things are true: - This attribute is present on every instance of the global (which means that the normal rule that the global must have a unique address can be broken without being observable by the program by performing comparisons against the global's address) - The global has linkonce_odr linkage (which means that each linkage unit must have its own copy of the global if it requires one, and the copy in each linkage unit must be the same) - It is a constant or a function (which means that the program cannot observe that the unique-address rule has been broken by writing to the global) Although this attribute could in principle be computed from the module contents, LTO clients (i.e. linkers) will normally need to be able to compute this property as part of symbol resolution, and it would be inefficient to materialize every module just to compute it. See: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160509/356401.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160516/356738.html for earlier discussion. Part of the fix for PR27553. Differential Revision: http://reviews.llvm.org/D20348 llvm-svn: 272709
* AMDGPU/SI: Refactor fixup handling for constant addrspace variablesTom Stellard2016-06-1413-47/+76
| | | | | | | | | | | | | | | | | | | | | | Summary: We now use a standard fixup type applying the pc-relative address of constant address space variables, and we have the GlobalAddress lowering code add the required 4 byte offset to the global address rather than doing it as part of the fixup. This refactoring will make it easier to use the same code for global address space variables and also simplifies the code. Re-commit this after fixing a bug where we were trying to use a reference to a Triple object that had already been destroyed. Reviewers: arsenm, kzhuravl Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21154 llvm-svn: 272705
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