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* Add PPC FP rounding instructions fri[mnpz]Hal Finkel2013-03-295-12/+64
| | | | | | | | | These instructions are available on the P5x (and later) and on the A2. They implement the standard floating-point rounding operations (floor, trunc, etc.). One caveat: frin (round to nearest) does not implement "ties to even", and so is only enabled in fast-math mode. llvm-svn: 178337
* [mips] Change type of accumulator registers to Untyped. Add two more accumulatorAkira Hatanaka2013-03-291-7/+30
| | | | | | | | register classes for Mips64 and DSP-ASE. No functionality changes. llvm-svn: 178328
* [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka2013-03-295-43/+74
| | | | | | No functionality changes. llvm-svn: 178327
* [mips] Add parameter Alignment to MipsFrameLowering's constructor.Akira Hatanaka2013-03-293-5/+4
| | | | | | No functionality changes. llvm-svn: 178326
* [Mips Assembler] Add support for OR macro with imediate opperandJack Carter2013-03-282-1/+6
| | | | | | | | | Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic llvm-svn: 178316
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-286-7/+51
| | | | llvm-svn: 178314
* Enhance boolean simplification to handle 16-/64-bit RDRANDMichael Liao2013-03-281-4/+9
| | | | | | | | | - RDRAND always clears the destination value when a random value is not available (i.e. CF == 0). This value is truncated or zero-extended as the false boolean value to be returned. Boolean simplification needs to skip this 'zext' or 'trunc' node. llvm-svn: 178312
* Skip moving call address loading into callseq when targets prefer register ↵Michael Liao2013-03-284-16/+7
| | | | | | | | | | | | | | | | | | indirect call. To enable a load of a call address to be folded with that call, this load is moved from outside of callseq into callseq. Such a moving adds a non-glued node (that load) into a glued sequence. This non-glue load is only removed when DAG selection folds them into a memory form call instruction. When such instruction selection is disabled, it breaks DAG schedule. To prevent that, such moving is disabled when target favors register indirect call. Previous workaround disabling CALL32m/CALL64m insn selection is removed. llvm-svn: 178308
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-282-0/+7
| | | | | | | | | | | Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic llvm-svn: 178304
* Add the X86 FMAs to the scheduling model.Nadav Rotem2013-03-282-2/+6
| | | | llvm-svn: 178303
* Add the Haswell machine model.Nadav Rotem2013-03-283-1/+128
| | | | llvm-svn: 178301
* Remove the unused port from the SandyBridge machine modelNadav Rotem2013-03-281-1/+0
| | | | llvm-svn: 178300
* Add ADX CPUID detectionMichael Liao2013-03-281-0/+4
| | | | llvm-svn: 178299
* These two are default in the constructor for MCAsmInfo.Eric Christopher2013-03-281-2/+0
| | | | llvm-svn: 178293
* Make Win32 put the SRet address into EAX, fixes PR15556Timur Iskhodzhanov2013-03-282-9/+16
| | | | llvm-svn: 178291
* Only enable 64-bit bswap DAG combines for PPC64Hal Finkel2013-03-281-0/+2
| | | | | | | | Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were added for bswap with load/store. This is because these combines are really only valid in 64-bit mode, regardless of the CPU (and this was not being checked). llvm-svn: 178286
* Hexagon: Replace switch-case in isDotNewInst with TSFlags.Jyotsna Verma2013-03-284-176/+26
| | | | llvm-svn: 178281
* Fix bad indentation in r178276Hal Finkel2013-03-281-2/+1
| | | | | | Thanks to Bill Schmidt for pointing this out! llvm-svn: 178280
* Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.Jyotsna Verma2013-03-281-0/+2
| | | | llvm-svn: 178279
* Use direct types in most PowerPC Altivec instructions and patterns.Bill Schmidt2013-03-281-236/+333
| | | | | | | | | | | | | | | | | | | | | | | This follows up Ulrich Weigand's work in PPCInstrInfo.td and PPCInstr64Bit.td by doing the corresponding work for most of the Altivec patterns. I have not been able to do anything for the following classes of instructions: (1) Vector logicals. These don't have corresponding intrinsics and don't have a single obvious vector type. So far as I can tell I need to leave these as VRRC. Affected instructions are: VAND, VANDC, VNOR, VOR, VXOR, V_SET0. (2) Instructions that make use of vector shuffle. The selection code promotes all shuffles to v16i8, so any pattern that matches on a shuffle is constrained. I haven't found any way to make the patterns match on their natural types, so I plan to leave these as VRRC. Affected instructions are: VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM, VPKUWUM. No change in behavior is anticipated. llvm-svn: 178277
* Add the PPC64 ldbrx/stdbrx instructionsHal Finkel2013-03-286-20/+37
| | | | | | | | These are 64-bit load/store with byte-swap, and available on the P7 and the A2. Like the similar instructions for 16- and 32-bit words, these are matched in the target DAG-combine phase against load/store-bswap pairs. llvm-svn: 178276
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-281-2/+2
| | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. llvm-svn: 178275
* Testing commit access to llvm. Remove two lines of whitespace from the ↵Gordon Keiser2013-03-281-2/+0
| | | | | | Thumb README. llvm-svn: 178256
* Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma2013-03-282-1094/+204
| | | | | | Remove noV4T gp-relative instructions. llvm-svn: 178246
* AArch64: implement GICv3 system registersTim Northover2013-03-282-5/+141
| | | | llvm-svn: 178236
* Add the PPC64 popcntd instructionHal Finkel2013-03-286-9/+23
| | | | | | | PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and tell TTI about it so that popcount-loop recognition will know about it. llvm-svn: 178233
* Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructionsHal Finkel2013-03-282-8/+8
| | | | | | | | There were a few places where kill flags were not being set correctly, and where 32-bit instruction variants were being used with 64-bit registers. After r178180, this code was being triggered causing llc to assert. llvm-svn: 178220
* Fix typo in PPCInstr64BitHal Finkel2013-03-281-1/+1
| | | | llvm-svn: 178219
* This patch follows is a follow up to r178171, which uses the register Preston Gurd2013-03-271-0/+9
| | | | | | | | | | | | | | form of call in preference to memory indirect on Atom. In this case, the patch applies the optimization to the code for reloading spilled registers. The patch also includes changes to sibcall.ll and movgs.ll, which were failing on the Atom buildbot after the first patch was applied. This patch by Sriram Murali. llvm-svn: 178193
* [ms-inline asm] Add support of imm displacement before bracketed memoryChad Rosier2013-03-271-15/+52
| | | | | | | | | | | | | | expression. Specifically, this syntax: ImmDisp [ BaseReg + Scale*IndexReg + Disp ] We don't currently support: ImmDisp [ Symbol ] rdar://13518671 llvm-svn: 178186
* Resynchronize isLoadFromStackSlot with LoadRegFromStackSlot (and stores) in ↵Hal Finkel2013-03-271-0/+18
| | | | | | | | | | | | | PPCInstrInfo These functions should have the same list of load/store instructions. Now that all load/store forms have been normalized (to single instructions or pseudos) they can be resynchronized. Found by inspection, although hopefully this will improve optimization. I've also added some comments. llvm-svn: 178180
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-274-1/+25
| | | | | | | | | | | | | indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. llvm-svn: 178171
* Fix typo (common to both X86 and PPC)Hal Finkel2013-03-272-2/+2
| | | | | | Thanks to Bill Schmidt for pointing this out during code review! llvm-svn: 178170
* Remove more dead LR-as-GPR PPC codeHal Finkel2013-03-271-16/+4
| | | | | | I had removed similar code a few days ago, but somehow missed this. llvm-svn: 178169
* Remove "gpr0 allocation" from the PPC README TODO listHal Finkel2013-03-271-1/+0
| | | | | | As Chris pointed out, post r178123, this is now done! llvm-svn: 178165
* R600/SI: add SETO/SETUO patternsChristian Konig2013-03-271-0/+14
| | | | | | | | 6 more piglit tests. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178145
* Print PPC ZERO as 0 (not r0) even on DarwinHal Finkel2013-03-271-2/+2
| | | | | | | It seems that the Darwin PPC assembler requires r0 to be written as 0 when it means 0 (at least in lwarx/stwcx.). Fixes PR15605. llvm-svn: 178142
* Switch to LLVM support function abs64 to keep VS2008 happy.Tim Northover2013-03-272-4/+4
| | | | llvm-svn: 178141
* Enabling the generation of dependency breakers for partial updates on ↵Silviu Baranga2013-03-272-9/+6
| | | | | | Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32. llvm-svn: 178134
* Hexagon: Disable optimizations at O0.Jyotsna Verma2013-03-271-18/+31
| | | | llvm-svn: 178132
* R600/SI: add cummuting of rev instructionsChristian Konig2013-03-275-34/+87
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178127
* R600/SI: add mulhu/mulhs patternsChristian Konig2013-03-273-2/+20
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178126
* R600/SI: add srl/sha patterns for SIChristian Konig2013-03-271-2/+6
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178125
* Allocate r0 on PPCHal Finkel2013-03-271-2/+0
| | | | | | | The R0 register can now be allocated because instructions that cannot use R0 as a GPR have been appropriately marked. llvm-svn: 178123
* Use the PPC no-r0 class on the TOC LD pseudosHal Finkel2013-03-271-2/+2
| | | | | | | | | | The register parameter in these instructions becomes the base register in an r+i ld instruction (and, thus, cannot be r0). This is not yet testable because we don't yet allocate r0 (and even then any test would be very fragile). llvm-svn: 178121
* Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudosHal Finkel2013-03-271-2/+7
| | | | | | | | | | Either operand of these pseudo instructions can be transformed into the first operand of an isel instruction (and this operand cannot be r0). This is not yet testable because we don't yet allocate r0 (and even when we do, any test would be very fragile). llvm-svn: 178119
* Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructionsHal Finkel2013-03-271-9/+9
| | | | | | | | | | | | Like the addi/addis instructions themselves, these pseudo instructions also cannot have r0 as their register parameter (because it will be interpreted as the value 0). This is not yet testable because we don't yet allocate r0 (and even when we do, any regression test would be very fragile because it would depend on the register allocator heuristics). llvm-svn: 178118
* Remove the link register from the GPR classes on PowerPC.Bill Schmidt2013-03-271-2/+2
| | | | | | | | | | | | | | | Some implementation detail in the forgotten past required the link register to be placed in the GPRC and G8RC register classes. This is just wrong on the face of it, and causes several extra intersection register classes to be generated. I found this was having evil effects on instruction scheduling, by causing the wrong register class to be consulted for register pressure decisions. No code generation changes are expected, other than some minor changes in instruction order. Seven tests in the test bucket required minor tweaks to adjust to the new normal. llvm-svn: 178114
* Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel2013-03-273-1/+8
| | | | | | | | | | | | | As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've added some asserts to make sure that we're not). As it turns out, we're not currently handling the Darwin case correctly (I've added a FIXME in the test case). I've tried adding various implied register definitions/uses to force the spill without success, so I'll need to address this later. llvm-svn: 178096
* Add XTEST codegen supportMichael Liao2013-03-264-1/+22
| | | | llvm-svn: 178083
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