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* [X86][SSE] Simplify zero'th index extract element matchingSimon Pilgrim2016-05-151-2/+3
| | | | llvm-svn: 269615
* [X86][SSE] Removed duplicate variables. NFCI.Simon Pilgrim2016-05-151-18/+10
| | | | | | Removed duplicate getOperand / getSimpleValueType calls. llvm-svn: 269614
* Move helper classes into anonymous namespaces. NFC.Benjamin Kramer2016-05-151-1/+1
| | | | llvm-svn: 269591
* [AVX512] Make the permd intrinsics take a 32-bit immediate to match the ↵Craig Topper2016-05-141-4/+4
| | | | | | software spec. llvm-svn: 269579
* ARM: support export directives for WindowsSaleem Abdulrasool2016-05-141-0/+23
| | | | | | | | | | It seems that cl will emit the export directives for Windows ARM targets. The fact that it did this had originally been missed and this functionality was never implemented. This makes it possible to rely solely on the source code for indicating what the exported interfaces are and brings us more compatibility with cl. llvm-svn: 269574
* [AArch64] Update local variable names to conform to coding standard. NFC.Chad Rosier2016-05-141-31/+31
| | | | llvm-svn: 269573
* Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512Elena Demikhovsky2016-05-142-107/+53
| | | | | | Differential revision http://reviews.llvm.org/D19261 llvm-svn: 269569
* [mips] Enable IAS by default for 32-bit MIPS targets (O32).Daniel Sanders2016-05-141-0/+5
| | | | | | | | | | | | | | | | | | | Summary: The MIPS IAS can now pass 'ninja check-all', recurse, build a bootable linux kernel, and pass a variety of LNT testing. Unfortunately we can't enable it by default for 64-bit targets yet since the N32 ABI is still very buggy and this also means we can't enable it for N64 either because we can't distinguish between N32 and N64 in the relevant code. Reviewers: vkalintiris Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D18759 Differential Revision: http://reviews.llvm.org/D18761 llvm-svn: 269560
* [WebAssembly] Fix legalization of i128 shifts.Dan Gohman2016-05-141-9/+4
| | | | | | | | compiler-rt/libgcc shift routines expect the shift count to be an i32, so use i32 as the shift count for shifts that are legalized to libcalls. This also reverts r268991, now that the signatures are correct. llvm-svn: 269531
* [AVX512] Fix types for pshufd intrinsics. The immediate is the second ↵Craig Topper2016-05-141-3/+3
| | | | | | | | argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file. Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs. llvm-svn: 269526
* [WebAssembly] Update expected torture test failuresDerek Schuff2016-05-141-2/+2
| | | | | | NFC; the waterfall just changed the way they are built. llvm-svn: 269523
* SDAG: Implement Select instead of SelectImpl in MipsDAGToDAGISelJustin Bogner2016-05-136-62/+54
| | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269519
* SDAG: Clean up a dead node I missed earlier in X86Justin Bogner2016-05-131-1/+1
| | | | | | H.J. Lu pointed out that I missed this in r269236. Thanks! llvm-svn: 269516
* [AArch64] Simplify logic to reduce vertical space. NFC.Chad Rosier2016-05-131-6/+2
| | | | llvm-svn: 269512
* SDAG: Implement Select instead of SelectImpl in XCoreDAGToDAGISelJustin Bogner2016-05-131-28/+38
| | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269509
* SDAG: Implement Select instead of SelectImpl in WebAssemblyDAGToDAGISelJustin Bogner2016-05-131-14/+4
| | | | | | | | | This backend doesn't do anything custom here yet, so we just modernize the boilerplate. Part of llvm.org/pr26808. llvm-svn: 269506
* SDAG: Implement Select instead of SelectImpl in SystemZDAGToDAGISelJustin Bogner2016-05-131-56/+56
| | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. Part of llvm.org/pr26808. llvm-svn: 269505
* SDAG: Implement Select instead of SelectImpl in SparcDAGToDAGISelJustin Bogner2016-05-131-16/+17
| | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269490
* SDAG: Implement Select instead of SelectImpl in NVPTXDAGToDAGISelJustin Bogner2016-05-132-213/+236
| | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. Part of llvm.org/pr26808. llvm-svn: 269483
* AMDGPU: Unify LowerGlobalAddressJan Vesely2016-05-133-18/+5
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19794 llvm-svn: 269481
* AMDGPU/R600: Fold global address operandJan Vesely2016-05-131-0/+7
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19793 llvm-svn: 269480
* AMDGPU/R600: Implement memory loads from constant ASJan Vesely2016-05-134-56/+33
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19792 llvm-svn: 269479
* AMDGPU/R600: Add support for emitting MCExprJan Vesely2016-05-132-1/+19
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19791 llvm-svn: 269478
* AMDGPU: Add support for MCExpr to instruction printerJan Vesely2016-05-132-3/+10
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19790 llvm-svn: 269477
* AMDGPU/R600: Use machine operands instead of ints to track literalsJan Vesely2016-05-131-19/+36
| | | | | | | | | | | | This will be used for global addresses Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19789 llvm-svn: 269476
* AMDGPU/R600: There are other uses for ALU_LITERAL besides ImmJan Vesely2016-05-131-3/+6
| | | | | | | | | | | | This will be used for GV Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19788 llvm-svn: 269475
* AMDGPU: Make CONST_DATA_PTR available to R600Jan Vesely2016-05-133-6/+6
| | | | | | | | | | | | Rename to AMDGPUconstdata_ptr Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19786 llvm-svn: 269474
* AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)Jan Vesely2016-05-133-1/+53
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19785 llvm-svn: 269473
* ARM: use callee-saved list in the order they're actually saved.Tim Northover2016-05-135-11/+29
| | | | | | | | | When setting the frame pointer, the offset from SP is calculated based on the stack slot it gets allocated, but this slot is in turn based on the order of the CSR list so that list should match the order we actually save the registers in. Mostly it did, but in the edge-case of MachO AAPCS targets it was wrong. llvm-svn: 269459
* [Hexagon] Remove dead nodes from SelectionDAG to avoid cyclesKrzysztof Parzyszek2016-05-131-1/+2
| | | | | | | | Recent changes to the instruction selection code exposed a problem where a dead node was not removed on time. This node had both input and output chains, which lead to an apparent cycle. llvm-svn: 269458
* [AMDGPU] Update nop insertion for debugger usageKonstantin Zhuravlyov2016-05-132-36/+15
| | | | | | | | | - Insert one nop for each high level statement instead of two - Do not insert nop before prologue Differential Revision: http://reviews.llvm.org/D20215 llvm-svn: 269452
* add support for -print-imm-hex for AArch64Paul Osmialowski2016-05-133-17/+26
| | | | | | | | | | | | | | | | | | | | | | | | | Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
* [scan-build] fix dead store warnings emitted on LLVM Hexagon code baseKrzysztof Parzyszek2016-05-134-4/+0
| | | | | | | | Patch by Apelete Seketeli. Differential Revision: http://reviews.llvm.org/D19900 llvm-svn: 269415
* [MIB] Create a helper function getRegState to extract all register flagsKrzysztof Parzyszek2016-05-131-12/+0
| | | | llvm-svn: 269414
* Assure calling "cld" instruction in prologue of X86 interrupt handler function.Amjad Aboud2016-05-131-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D18725 llvm-svn: 269413
* [mips][ias] Work around yet another incorrect microMIPS relocation ↵Daniel Sanders2016-05-131-3/+7
| | | | | | | | | | | | evaluation exposed by r268900. It's not entirely clear why R_MICROMIPS_(GOT|HI16|LO16) are evaluated incorrectly in a small number of the LNT tests at this point. However, it's not related to the STO_MIPS_MICROMIPS issue. At this point all the microMIPS-related changes of r268900 have been reverted. llvm-svn: 269410
* [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and ↵Hrvoje Varga2016-05-139-5/+92
| | | | | | | | MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
* SDAG: Clean up a dangling node in SparcISelDAGToDAG::SelectImplJustin Bogner2016-05-131-0/+1
| | | | | | | | | When we convert to the void Select interface, leaving unreferenced nodes around won't be allowed anymore. Part of llvm.org/pr26808. llvm-svn: 269396
* SDAG: Clean up a dangling node in MipsISelDAGToDAG::SelectImplJustin Bogner2016-05-131-0/+1
| | | | | | | | | When we convert to the void Select interface, leaving unreferenced nodes around won't be allowed anymore. Part of llvm.org/pr26808. llvm-svn: 269394
* SDAG: Implement Select instead of SelectImpl in MSP430DAGToDAGISelJustin Bogner2016-05-131-76/+57
| | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269393
* AMDGPU: Remove verifier check for scc live insMatt Arsenault2016-05-131-10/+0
| | | | | | | | | | We only really need this to be true for SIFixSGPRCopies. I'm not sure there's any way this could happen before that point. Fixes a case where MachineCSE could introduce a cross block scc use. llvm-svn: 269391
* SDAG: Implement Select instead of SelectImpl in AArch64DAGToDAGISelJustin Bogner2016-05-121-802/+1161
| | | | | | | | | | | | | | This one has a lot of code churn, but it's all mechanical and straightforward. - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269379
* SDAG: Implement Select instead of SelectImpl in LanaiDAGToDAGISelJustin Bogner2016-05-121-21/+13
| | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269364
* SDAG: Implement Select instead of SelectImpl in HexagonDAGToDAGISelJustin Bogner2016-05-121-139/+189
| | | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we had already replaced all uses and we returned a node, just remove the dead node instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. Part of llvm.org/pr26808. llvm-svn: 269358
* SDAG: Clean up a dangling node in HexagonISelDAGToDAG::SelectImplJustin Bogner2016-05-121-1/+1
| | | | | | | | | When we convert to the void Select interface, leaving unreferenced nodes around won't be allowed anymore. Part of llvm.org/pr26808. llvm-svn: 269355
* [ARM] Support and tests for transform of LDR rt, = to MOVRenato Golin2016-05-121-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | This change implements the transformation in processInstruction() for the LDR rt, =expression to MOV rt, expression when the expression can be evaluated and can fit into the immediate field of the MOV or a MVN. Across the ARM and Thumb instruction sets there are several cases to consider, each with a different range of representatble constants. In ARM we have: * Modified immediate (All ARM architectures) * MOVW (v6t2 and above) In Thumb we have: * Modified immediate (v6t2, v7m and v8m.mainline) * MOVW (v6t2, v7m, v8.mainline and v8m.baseline) * Narrow Thumb MOV that can be used in an IT block (non flag-setting) If the immediate fits any of the available alternatives then we make the transformation. Fixes 25722. Patch by Peter Smith. llvm-svn: 269354
* [ARM] Delay ARM constant pool creation. NFC.Renato Golin2016-05-125-6/+92
| | | | | | | | | | | | | | | | | | | | | This change adds a new constant pool kind to ARMOperand. When parsing the operand for =immediate we create an instance of this operand rather than creating a constant pool entry and rewriting the operand. As the new operand kind is only created for ldr rt,= we can make ldr rt,= an explicit pseudo instruction in ARM, Thumb and Thumb2 The pseudo instruction is expanded in processInstruction(). This creates the constant pool and transforms the pseudo instruction into a pc-relative ldr to the constant pool. There are no functional changes and no modifications needed to existing tests. Required by the patch that fixes PR25722. Patch by Peter Smith. llvm-svn: 269352
* SDAG: Implement Select instead of SelectImpl in BPFDAGToDAGISelJustin Bogner2016-05-121-15/+10
| | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269350
* SDAG: Implement Select instead of SelectImpl in AMDGPUDAGToDAGISelJustin Bogner2016-05-121-49/+67
| | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269349
* SDAG: Clean up dangling nodes in AArch64ISelDAGToDAG::SelectImplJustin Bogner2016-05-121-5/+8
| | | | | | | | | When we convert to the void Select interface, leaving unreferenced nodes around won't be allowed anymore. Part of llvm.org/pr26808. llvm-svn: 269345
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