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* AArch64: work around ld64 bug more aggressively.Tim Northover2015-05-181-5/+4
| | | | | | | | | | | | | | | ld64 currently mishandles internal pointer relocations (i.e. ARM64_RELOC_UNSIGNED referred to by section & offset rather than symbol). The existing __cfstring clause was an early discovery and workaround for this, but the problem is wider and we should avoid such relocations wherever possible for now. This code should be reverted to allowing internal relocations as soon as possible. PR23437. llvm-svn: 237621
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-1811-37/+37
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-1843-137/+137
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* ARM: allow jump tables to be placed as constant islands.Tim Northover2015-05-187-170/+312
| | | | | | | | | | | | | | | | | Previously, they were forced to immediately follow the actual branch instruction. This was usually OK (the LEAs actually accessing them got emitted nearby, and weren't usually separated much afterwards). Unfortunately, a sufficiently nasty phi elimination dumps many instructions right before the basic block terminator, and this can increase the range too much. This patch frees them up to be placed as usual by the constant islands pass, and consequently has to slightly modify the form of TBB/TBH tables to refer to a PC-relative label at the final jump. The other jump table formats were already position-independent. rdar://20813304 llvm-svn: 237590
* Sparc: support the "set" synthetic instruction.James Y Knight2015-05-183-2/+74
| | | | | | | | | This pseudo-instruction expands into 'sethi' and 'or' instructions, or, just one of them, if the other isn't necessary for a given value. Differential Revision: http://reviews.llvm.org/D9089 llvm-svn: 237585
* Revert r237579, as it broke windows buildbotsOliver Stannard2015-05-186-611/+18
| | | | llvm-svn: 237583
* Sparc: Support PSR, TBR, WIM read/write instructions.James Y Knight2015-05-183-8/+87
| | | | | | Differential Revision: http://reviews.llvm.org/D8971 llvm-svn: 237582
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-185-15/+69
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-185-20/+92
| | | | | | | | | | (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
* [LLVM - ARM/AArch64] Add ACLE special register intrinsicsOliver Stannard2015-05-186-18/+611
| | | | | | | | | | | | | | | | | | | This patch implements LLVM support for the ACLE special register intrinsics in section 10.1, __arm_{w,r}sr{,p,64}. This patch is intended to lower the read/write_register instrinsics, used to implement the special register intrinsics in the clang patch for special register intrinsics (see http://reviews.llvm.org/D9697), to ARM specific instructions MRC,MCR,MSR etc. to allow reading an writing of coprocessor registers in AArch32 and AArch64. This is done by inspecting the register string passed to the intrinsic and then lowering to the appropriate instruction. Patch by Luke Cheeseman. Differential Revision: http://reviews.llvm.org/D9699 llvm-svn: 237579
* [mips][microMIPSr6] Implement ALIGN and AUI instructionsJozef Kolek2015-05-183-4/+59
| | | | | | | | This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
* AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/DElena Demikhovsky2015-05-182-2/+27
| | | | | | | | | instructions. These intrinsics are comming with rounding mode. Added intrinsics for MAXSS/D, MINSS/D - with and without sae. By Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 237560
* fixed compilation warning/errorElena Demikhovsky2015-05-181-0/+1
| | | | llvm-svn: 237559
* AVX-512: Added patterns for scalar-to-vector broadcastElena Demikhovsky2015-05-181-0/+10
| | | | llvm-svn: 237558
* AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other ↵Elena Demikhovsky2015-05-183-12/+61
| | | | | | | | instructions from this set Added encoding tests. llvm-svn: 237557
* [PowerPC] Add extra r2 read deps on @toc@l relocationsHal Finkel2015-05-184-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If some commits are happy, and some commits are sad, this is a sad commit. It is sad because it restricts instruction scheduling to work around a binutils linker bug, and moreover, one that may never be fixed. On 2012-05-21, GCC was updated not to produce code triggering this bug, and now we'll do the same... When resolving an address using the ELF ABI TOC pointer, two relocations are generally required: one for the high part and one for the low part. Only the high part generally explicitly depends on r2 (the TOC pointer). And, so, we might produce code like this: .Ltmp526: addis 3, 2, .LC12@toc@ha .Ltmp1628: std 2, 40(1) ld 5, 0(27) ld 2, 8(27) ld 11, 16(27) ld 3, .LC12@toc@l(3) rldicl 4, 4, 0, 32 mtctr 5 bctrl ld 2, 40(1) And there is nothing wrong with this code, as such, but there is a linker bug in binutils (https://sourceware.org/bugzilla/show_bug.cgi?id=18414) that will misoptimize this code sequence to this: nop std r2,40(r1) ld r5,0(r27) ld r2,8(r27) ld r11,16(r27) ld r3,-32472(r2) clrldi r4,r4,32 mtctr r5 bctrl ld r2,40(r1) because the linker does not know (and does not check) that the value in r2 changed in between the instruction using the .LC12@toc@ha (TOC-relative) relocation and the instruction using the .LC12@toc@l(3) relocation. Because it finds these instructions using the relocations (and not by scanning the instructions), it has been asserted that there is no good way to detect the change of r2 in between. As a result, this bug may never be fixed (i.e. it may become part of the definition of the ABI). GCC was updated to add extra dependencies on r2 to instructions using the @toc@l relocations to avoid this problem, and we'll do the same here. This is done as a separate pass because: 1. These extra r2 dependencies are not really properties of the instructions, but rather due to a linker bug, and maybe one day we'll be able to get rid of them when targeting linkers without this bug (and, thus, keeping the logic centralized here will make that straightforward). 2. There are ISel-level peephole optimizations that propagate the @toc@l relocations to some user instructions, and so the exta dependencies do not apply only to a fixed set of instructions (without undesirable definition replication). The test case was reduced with the help of bugpoint, with minimal cleaning. I'm looking forward to our upcoming MI serialization support, and with that, much better tests can be created. llvm-svn: 237556
* AVX-512: fixed extended load to 512-bit registerElena Demikhovsky2015-05-171-2/+2
| | | | llvm-svn: 237537
* AVX-512: fixed a bug in mask operations - (i1 1) patternElena Demikhovsky2015-05-171-2/+2
| | | | | | | Filling k-reg with all-ones value was wrong, (i1 1) should switch on only one bit in mask register llvm-svn: 237536
* [x86] Distinguish the 'o', 'v', 'X', and 'i' inline assembly memory constraints.Daniel Sanders2015-05-162-3/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: But still handle them the same way since I don't know how they differ on this target. Of these, 'o' and 'v' are not tested but were already implemented. I'm not sure why 'i' is required for X86 since it's supposed to be an immediate constraint rather than a memory constraint. A test asserts without it so I've included it for now. No functional change intended. Reviewers: nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8254 llvm-svn: 237517
* MC: Use MCSymbol in RelAndSymbol, NFCDuncan P. N. Exon Smith2015-05-164-22/+14
| | | | | | Switch from `MCSymbolData` to `MCSymbol`. llvm-svn: 237502
* [PPC64] Add vector pack/unpack support from ISA 2.07Bill Schmidt2015-05-164-2/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following new instructions in the Power ISA 2.07: vpksdss vpksdus vpkudus vpkudum vupkhsw vupklsw These instructions are available through the vec_packs, vec_packsu, vec_unpackh, and vec_unpackl built-in interfaces. These are lane-sensitive instructions, so the built-ins have different implementations for big- and little-endian, and the instructions must be marked as killing the vector swap optimization for now. The first three instructions perform saturating pack operations. The fourth performs a modulo pack operation, which means it can be represented with a vector shuffle, and conversely the appropriate vector shuffles may cause this instruction to be generated. The other instructions are only generated via built-in support for now. Appropriate tests have been added. There is a companion patch to clang for the rest of this support. llvm-svn: 237499
* MC: Change MCFragment::Atom to an MCSymbol, NFCDuncan P. N. Exon Smith2015-05-162-32/+41
| | | | | | | Change `MCFragment::Atom` from an `MCSymbolData` to an `MCSymbol`, moving in the direction of removing the back-pointer. llvm-svn: 237497
* Remove MCAssembler.h include from MCStreamer.h and fix users of MCStreamer.hPete Cooper2015-05-154-0/+4
| | | | llvm-svn: 237483
* Remove 3 includes from MCInstrDesc.h and explicitly include them where neededPete Cooper2015-05-1513-0/+20
| | | | llvm-svn: 237481
* [X86] Use a better sentinel offset for the FrameAddr indexDavid Majnemer2015-05-151-1/+1
| | | | | | | | | Other pieces of CodeGen want to negate frame object offsets to account for architectures where the stack grows down. Our object is a pseudo object so it's offset doesn't matter. However, we shouldn't choose an offset which results in undefined behavior if you negate it. llvm-svn: 237474
* MC: MCCodeGenInfo naming update. NFC.Jim Grosbach2015-05-1513-14/+14
| | | | | | s/InitMCCodeGenInfo/initMCCodeGenInfo/ llvm-svn: 237471
* MC: Update MCCodeEmitter naming. NFC.Jim Grosbach2015-05-1515-26/+26
| | | | | | s/EncodeInstruction/encodeInstruction/ llvm-svn: 237469
* MC: Update MCFixup naming. NFC.Jim Grosbach2015-05-1511-55/+55
| | | | | | s/MCFixup::Create/MCFixup::create/ llvm-svn: 237468
* Mark SMIN/SMAX/UMIN/UMAX nodes as legal and add patterns for them.James Molloy2015-05-152-0/+55
| | | | | | | The new [SU]{MIN,MAX} SDNodes can be lowered directly to instructions for most NEON datatypes - the big exclusion being v2i64. llvm-svn: 237455
* [xcore] Only support the 'm' inline assembly memory constraint. NFC.Daniel Sanders2015-05-151-6/+0
| | | | | | | | | | | | | | | | | | Summary: XCore doesn't seem to have any additional constraints. Therefore remove the target hook. No functional change intended. Reviewers: friedgold Reviewed By: friedgold Subscribers: friedgold, llvm-commits Differential Revision: http://reviews.llvm.org/D8921 llvm-svn: 237442
* [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.Toma Tabacu2015-05-151-5/+18
| | | | | | | | | | | | | | | | | | Summary: To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI. This currently happens because of sign extension. To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8662 llvm-svn: 237428
* Stop resetting SanitizeAddress in TargetMachine::resetTargetOptions. NFC.Akira Hatanaka2015-05-151-2/+0
| | | | | | | | | | | | | | Instead of doing that, create a temporary copy of MCTargetOptions and reset its SanitizeAddress field based on the function's attribute every time an InlineAsm instruction is emitted in AsmPrinter::EmitInlineAsm. This is part of the work to remove TargetMachine::resetTargetOptions (the FIXME added to TargetMachine.cpp in r236009 explains why this function has to be removed). Differential Revision: http://reviews.llvm.org/D9570 llvm-svn: 237412
* Remove setting FloatABIType from the X86 port, nothing uses it.Eric Christopher2015-05-141-4/+0
| | | | llvm-svn: 237398
* [Hexagon] Generate hardware loop for a vectorized loopBrendon Cahoon2015-05-141-7/+46
| | | | | | | | | The induction variable in the vectorized loop wasn't recognized properly, so a hardware loop wasn't generated. Differential Revision: http://reviews.llvm.org/D9722 llvm-svn: 237388
* [Hexagon] Remove dead constant assignment in hardware loop passBrendon Cahoon2015-05-141-3/+9
| | | | | | | | | | | After converting a loop to a hardware loop, the pass should remove any unnecessary instructions from the old compare-and-branch code. This patch removes a dead constant assignment that was used in the compare instruction. Differential Revision: http://reviews.llvm.org/D9720 llvm-svn: 237373
* Reflow long lines of some LLVMBuild filesDouglas Katzman2015-05-141-1/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D9752 llvm-svn: 237367
* [mips] [IAS] Enforce .set nomacro.Toma Tabacu2015-05-141-0/+10
| | | | | | | | | | | | | | Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9564 llvm-svn: 237366
* [Hexagon] Check for underflow/wrap in hardware loop passBrendon Cahoon2015-05-141-55/+307
| | | | | | | | If the loop trip count may underflow or wrap, the compiler should not generate a hardware loop since the trip count will be incorrect. llvm-svn: 237365
* [mips] [IAS] Emit .set macro/nomacro.Toma Tabacu2015-05-141-0/+2
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
* [mips] Do not place users of $ra in the delay slot of call instructions.Vasileios Kalintiris2015-05-141-0/+8
| | | | | | | | | | | | | | | Summary: When we are trying to fill the delay slot of a call instruction, we must avoid filler instructions that use the $ra register. This fixes the test MultiSource/Applications/JM/lencod when we enable the forward delay slot filler. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9670 llvm-svn: 237362
* Re-apply r237247 - [AArch64] Codegen VMAX/VMIN for safe math casesArtyom Skrobov2015-05-142-44/+74
| | | | | | No longer breaks SPEC2000/2006 llvm-svn: 237361
* [mips] [IAS] Warn when LA is used with a 64-bit symbol.Toma Tabacu2015-05-141-8/+11
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9295 llvm-svn: 237356
* [mips] [IAS] Give expandLoadAddressSym() more specific arguments. NFC.Toma Tabacu2015-05-141-23/+13
| | | | | | | | | | | | | | | | Summary: If we only pass the necessary operands, we don't have to determine the position of the symbol operand when entering expandLoadAddressSym(). This simplifies the expandLoadAddressSym() code. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9291 llvm-svn: 237355
* [AArch64] Slight naming changes and comments for AArch64NamedImmMapperVladimir Sukharev2015-05-141-4/+7
| | | | | | | | | | | | Reviewers: echristo Subscribers: llvm-commits Follow-up to: http://reviews.llvm.org/D8496#158595 Relates to: http://reviews.llvm.org/rL235089 llvm-svn: 237354
* AVX-512: Added i1 type handling for calling conventions.Elena Demikhovsky2015-05-142-21/+31
| | | | | | | | i1 type is a legal type on AVX-512 and can be passed as parameter or return value. i1 is promoted to i8 on return and to i32 for call arguments (i8 is also promoted to i32 here). The result code is similar to the previous X86 targets, where i1 is allways promoted to i8. llvm-svn: 237350
* [X86] Fix PR23271 - RIP-relative decoding bug in disassembler.Douglas Katzman2015-05-131-9/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
* ARM: remove possible vestiges of the legacy JIT???Tim Northover2015-05-132-11/+6
| | | | | | | | There's no need to manually pass modifier strings around to tell an operand how to print now, that information is encoded in the operand itself since the MC layer came along. llvm-svn: 237295
* ARM: remove custom jump table UIDTim Northover2015-05-1310-82/+53
| | | | | | | | We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
* ARM: refactor optimizeThumb2JumpTables.Tim Northover2015-05-131-59/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | The previous logic mixed 2 separate questions: + Can we form a TBB/TBH instruction? + Can we remove the jump-table calculation before it? It then performed a bunch of random tests on the instructions earlier in the basic block, which were probably sufficient to answer 2 but only because of the very limited ways in which a t2BR_JT can actually be created. For example there's no reason to expect the LeaInst to define the same base register as the following indexing calulation. In practice this means we might have missed opportunities to form TBB/TBH, in theory you could end up misidentifying a sequence and removing the wrong LEA: %R1 = t2LEApcrelJT ... %R2 = t2LEApcrelJT ... <... using and killing %R2 ...> %R2 = t2ADDr %R1, $Ridx Before we would have looked for an LEA defining %R2 and found the wrong one. We just got lucky that jump table setup was (almost?) always confined to a single basic block and there was only one jump table per block. llvm-svn: 237293
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-1349-1175/+1174
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
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