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* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-132-1/+45
| | | | | | rdar://10549767 llvm-svn: 146520
* ARM LDM/STM system instruction variants.Jim Grosbach2011-12-132-11/+39
| | | | | | rdar://10550269 llvm-svn: 146519
* Thumb2 pre/post indexed stores can be from any non-PC GPR.Jim Grosbach2011-12-131-3/+3
| | | | | | rdar://10549786 llvm-svn: 146518
* Thumb2 tweak for ccout handling in RSB parsing.Jim Grosbach2011-12-131-1/+4
| | | | llvm-svn: 146516
* ARM thumb2 parsing of "rsb rd, rn, #0".Jim Grosbach2011-12-131-2/+8
| | | | | | rdar://10549741 llvm-svn: 146515
* ARM NEON two-operand aliases for VQDMULH.Jim Grosbach2011-12-132-0/+13
| | | | llvm-svn: 146514
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-133-3/+13
| | | | llvm-svn: 146511
* ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-132-0/+3
| | | | llvm-svn: 146508
* ARM add more 'gas' compatibility aliases for NEON instructions.Jim Grosbach2011-12-133-3/+37
| | | | llvm-svn: 146507
* [fast-isel] Unaligned loads of floats are not supported. Therefore, convert ↵Chad Rosier2011-12-131-7/+32
| | | | | | | | to a regular load and then move the result from a GPR to a FPR. llvm-svn: 146502
* Expand .cprestore directive to multiple instructions if the offset does not fit Akira Hatanaka2011-12-133-16/+35
| | | | | | in a 16-bit field. llvm-svn: 146469
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-1310-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Account for CPE alignment when searching for new water.Jakob Stoklund Olesen2011-12-131-31/+51
| | | | | | | | | | | Constant pool entries with different alignment may cause more alignment padding to be inserted. Compute the amount of padding needed, and try to pick the location that requires the least amount of padding. Also take the extra padding into account when the water is above the use. llvm-svn: 146458
* Target/Hexagon: Fix CMake build. We don't use add_llvm_library_dependencies().NAKAMURA Takumi2011-12-132-16/+0
| | | | llvm-svn: 146457
* LLVMBuild: Introduce a common section which currently has a list of theDaniel Dunbar2011-12-1215-3/+43
| | | | | | | | | | | subdirectories to traverse into. - Originally I wanted to avoid this and just autoscan, but this has one key flaw in that new subdirectories can not automatically trigger a rerun of the llvm-build tool. This is particularly a pain when switching back and forth between trees where one has added a subdirectory, as the dependencies will tend to be wrong. This will also eliminates FIXME implicitly. llvm-svn: 146436
* Emit B (unconditional branch) when -relocation-model=pic and J (jump) whenAkira Hatanaka2011-12-123-8/+25
| | | | | | -relocation-model=static. llvm-svn: 146432
* Fix indentation.Akira Hatanaka2011-12-121-1/+1
| | | | llvm-svn: 146431
* fix warningTony Linthicum2011-12-121-1/+1
| | | | llvm-svn: 146420
* Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>Bob Wilson2011-12-121-4/+14
| | | | | | | | | These modifiers simply select either the low or high D subregister of a Neon Q register. I've also removed the unimplemented 'p' modifier, which turns out to be a bit different than the comment here suggests and as far as I can tell was only intended for internal use in Apple's version of gcc. llvm-svn: 146417
* Hexagon backend supportTony Linthicum2011-12-1254-0/+20764
| | | | llvm-svn: 146412
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-1248-48/+0
| | | | llvm-svn: 146409
* XOP instructions and encoding tests.Jan Sjödin2011-12-123-0/+265
| | | | llvm-svn: 146407
* Add a postOffset() alignment argument.Jakob Stoklund Olesen2011-12-121-14/+15
| | | | | | | This computes the offset of the layout sucessor block, considering its alignment as well. llvm-svn: 146401
* Fix typo.Jakob Stoklund Olesen2011-12-121-1/+1
| | | | llvm-svn: 146400
* XOP encoding bits and logic.Jan Sjödin2011-12-123-5/+44
| | | | llvm-svn: 146397
* Also set the proper alignment on inner islands and the function itself.Jakob Stoklund Olesen2011-12-121-15/+29
| | | | | | | | | Downgrade the alignment of the initial constant island when constant pool entries are moved elsewhere. This is all gated by -arm-align-constant-islands. llvm-svn: 146391
* Make MF a class member instead of passing it around everywhere.Jakob Stoklund Olesen2011-12-121-81/+77
| | | | | | | | Also add an MCP member pointing to the machine constant pool. No functional change intended. llvm-svn: 146382
* Add a -arm-align-constant-islands flag, default off.Jakob Stoklund Olesen2011-12-121-9/+35
| | | | | | | | | | | | Order constant pool entries by descending alignment in the initial island to ensure packing and correct alignment. When the command line flag is set, also align the basic block containing the constant pool entries. This is only a partial implementation of constant island alignment. More to come. llvm-svn: 146375
* Remove some remants of the old palign pattern fragment that were still ↵Craig Topper2011-12-113-20/+7
| | | | | | hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast. llvm-svn: 146344
* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-111-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. llvm-svn: 146341
* Mips: Don't create a dangling IR function just to get the address of a symbol.Benjamin Kramer2011-12-111-6/+1
| | | | llvm-svn: 146340
* Also remove unnecessary includes from this file, which was supposed to be partNick Lewycky2011-12-111-2/+0
| | | | | | of r146334! llvm-svn: 146338
* Minimize #include's and forward-declares in Target.Nick Lewycky2011-12-101-2/+0
| | | | llvm-svn: 146335
* Refactor the implementation of the TargetOptions out of TargetMachine, takingNick Lewycky2011-12-103-33/+53
| | | | | | the only parts of TM that depends on CodeGen headers with it. llvm-svn: 146334
* Revert r146322 to appease buildbots. Original commit message:Chad Rosier2011-12-101-22/+0
| | | | | | | | Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. llvm-svn: 146328
* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-101-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. llvm-svn: 146322
* Make CR spill and restore use a reserved register. These operations cannot ↵Hal Finkel2011-12-101-10/+18
| | | | | | use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. llvm-svn: 146318
* Try to align the point where a large basic block is split.Jakob Stoklund Olesen2011-12-101-11/+50
| | | | | | | | | | | | | | | | The split point is picked such that the newly created water has the same alignment as the function. This makes the island suitable for constant pool entries with potentially higher alignment. This also fixes an issue where the basic block was split one instruction too late, causing nonconvergence of the algorithm. <rdar://problem/10550705> There is still an issue with correctly packing differently aligned entries in the island. llvm-svn: 146314
* More debug output formatting.Jakob Stoklund Olesen2011-12-101-9/+20
| | | | llvm-svn: 146313
* Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gasRafael Espindola2011-12-101-12/+28
| | | | | | | | does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC, but it doesn't change the immediate in the same way as when the expression has no right hand side symbol. llvm-svn: 146311
* ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-102-1/+21
| | | | llvm-svn: 146300
* Splats can contain undef's; make sure to handle them correctly. PR11526.Eli Friedman2011-12-091-2/+1
| | | | llvm-svn: 146299
* ARM add some pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-093-6/+31
| | | | llvm-svn: 146296
* ARM allows '' syntax, not just '#imm' for assembly.Jim Grosbach2011-12-091-10/+21
| | | | | | | | Backwards compatibility with 'gas'. #imm is the preferered and documented syntax, but lots of existing code uses the '$' prefix, so we should support it if we can. llvm-svn: 146285
* ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach2011-12-092-0/+27
| | | | | | | | | | | When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
* ARM NEON data type aliases for VBIC(register).Jim Grosbach2011-12-091-1/+9
| | | | llvm-svn: 146281
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-095-67/+139
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* User a helper overload for a common pattern.Jakob Stoklund Olesen2011-12-091-8/+11
| | | | llvm-svn: 146270
* Tidy up. Better base class factoring.Jim Grosbach2011-12-091-21/+13
| | | | llvm-svn: 146267
* Tidy up. Better base class factoring.Jim Grosbach2011-12-091-20/+12
| | | | llvm-svn: 146266
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