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* [PATCH] [mips] Fix forbidden slot hazard handlingSimon Dardis2016-04-291-3/+11
| | | | | | | | | | | | | | | | | | MipsHazardSchedule has to determine what the next physical machine instruction is to decide whether to insert a nop. In case where a branch with a forbidden slot appears at the end of a basic block, first *real* instruction of the next physical basic block was determined using getFirstNonDebugInstr(). Unfortunately this only considers DBG_VALUEs and not other transient opcodes such as EHLABEL. As EHLABEL passes the SafeInForbiddenSlot predicate and the instruction after the EHLABEL can be a CTI, we observed test failures in the LNT testsuite. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19051 llvm-svn: 268052
* [Hexagon] Optimize addressing modes for load/storeKrzysztof Parzyszek2016-04-298-1/+848
| | | | | | Patch by Jyotsna Verma. llvm-svn: 268051
* Unify XDEBUG and EXPENSIVE_CHECKS (into the latter), and add an option to ↵Filipe Cabecinhas2016-04-294-5/+5
| | | | | | | | | | | | | | | | | | | the cmake build to enable them. Summary: Historically, we had a switch in the Makefiles for turning on "expensive checks". This has never been ported to the cmake build, but the (dead-ish) code is still around. This will also make it easier to turn it on in buildbots. Reviewers: chandlerc Subscribers: jyknight, mzolotukhin, RKSimon, gberry, llvm-commits Differential Revision: http://reviews.llvm.org/D19723 llvm-svn: 268050
* AMDGPU/SI: Add offset field to ds_permute/ds_bpermute instructionsTom Stellard2016-04-293-12/+8
| | | | | | | | | | | | | | Summary: These instructions can add an immediate offset to the address, like other ds instructions. Reviewers: arsenm Subscribers: arsenm, scchan Differential Revision: http://reviews.llvm.org/D19233 llvm-svn: 268043
* [mips][ias] Split expandMemInst between MipsAsmParser and ↵Daniel Sanders2016-04-293-66/+205
| | | | | | | | | | | | | | | | | | | | | | MipsTargetStreamer. Almost NFC. Summary: The portion in MipsAsmParser is responsible for figuring out which expansion to use, while the portion in MipsTargetStreamer is responsible for emitting it. This allows us to remove the call to isIntegratedAssemblerRequired() which is currently ensuring the effect of .cprestore only occurs when writing objects. The small functional change is that the memory offsets are now correctly printed as signed values. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19714 llvm-svn: 268042
* [mips][ias] Moved most instruction emission helpers to MipsTargetStreamer. NFC.Daniel Sanders2016-04-293-279/+325
| | | | | | | | | | | | | | | | | | | Summary: * Moved all the emit*() helpers to MipsTargetStreamer. * Moved createNop() to MipsTargetStreamer as emitNop() and emitEmptyDelaySlot(). This instruction has been split to distinguish between the 'nop' instruction and the nop used in delay slots which is sometimes a different nop to the 'nop' instruction (e.g. for short delay slots on microMIPS). * Moved createAddu() to MipsTargetStreamer as emitAddu(). * Moved createAppropriateDSLL() to MipsTargetStreamer as emitDSLL(). Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19712 llvm-svn: 268041
* [mips][ias] Make section sizes a multiple of the alignment.Daniel Sanders2016-04-291-0/+15
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19008 llvm-svn: 268036
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-294-622/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
* [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructionsZlatko Buljan2016-04-294-33/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
* AMDGPU: Stop reporting an addressing mode for unknown addrspaceMatt Arsenault2016-04-291-1/+6
| | | | | | | | | This was being treated the same as private, which has an immediate offset. For unknown, it probably means it's for a computation not actually being used for accessing memory, so it should not have a nontrivial addressing mode. llvm-svn: 268002
* [X86] Remove unnecessary header file containing a small class. It was only ↵Craig Topper2016-04-292-115/+84
| | | | | | included in one place. Just define the class directly in the cpp file. NFC llvm-svn: 267985
* [X86] Include X86MCTargetDesc.h directly in X86Disassembler.cpp instead of ↵Craig Topper2016-04-291-9/+1
| | | | | | duplicating parts of it. NFC llvm-svn: 267984
* [X86] Use nested switches to vary the operand to helper functions that were ↵Craig Topper2016-04-291-43/+74
| | | | | | previously called in multiple cases. This seems to help the inliner reduce code. NFC llvm-svn: 267964
* LiveIntervalAnalysis: Remove LiveVariables requirementMatthias Braun2016-04-281-1/+8
| | | | | | | | | | | | This requirement was a huge hack to keep LiveVariables alive because it was optionally used by TwoAddressInstructionPass and PHIElimination. However we have AnalysisUsage::addUsedIfAvailable() which we can use in those passes. This re-applies r260806 with LiveVariables manually added to PowerPC to hopefully not break the stage 2 bots this time. llvm-svn: 267954
* [PowerPC] Fix the EH_SjLj_Setup pseudo.Marcin Koscielnicki2016-04-282-1/+6
| | | | | | | | | | | | | | | | | | | This instruction is just a control flow marker - it should not actually exist in the object file. Unfortunately, nothing catches it before it gets to AsmPrinter. If integrated assembler is used, it's considered to be a normal 4-byte instruction, and emitted as an all-0 word, crashing the program. With external assembler, a comment is emitted. Fixed by setting Size to 0 and handling it in MCCodeEmitter - this means the comment will still be emitted if integrated assembler is not used. This broke an ASan test, which has been disabled for a long time as a result (see the discussion on D19657). We can reenable it once this lands. llvm-svn: 267943
* [RDF] Recognize tail calls in graph creationKrzysztof Parzyszek2016-04-281-4/+20
| | | | llvm-svn: 267939
* [RDF] Improve handling of inline-asmKrzysztof Parzyszek2016-04-281-4/+5
| | | | | | | - Keep implicit defs from inline-asm instructions. - Treat register references from inline-asm as fixed. llvm-svn: 267936
* [RDF] Add option to keep dead phi nodes in DFGKrzysztof Parzyszek2016-04-283-4/+15
| | | | | | | | | | Dead phi nodes are needed for code motion (such as copy propagation), where a new use would be placed in a location that would be dominated by a dead phi. Such a transformation is not legal for copy propagation, and the existence of the phi would prevent it, but if the phi is not there, it may appear to be valid. llvm-svn: 267932
* This reverts commit r265505.Kit Barton2016-04-287-268/+0
| | | | | | | Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance". This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe. llvm-svn: 267927
* [Hexagon] Add instruction aliases for vector unsigned compare-equalKrzysztof Parzyszek2016-04-281-0/+65
| | | | | | Unsigned compare-equal instructions are mapped to signed compare-equal. llvm-svn: 267925
* AMDGPU: Emit error if too much LDS is usedMatt Arsenault2016-04-281-0/+5
| | | | llvm-svn: 267922
* AMDGPU: Fix mishandling array allocations when promoting allocaMatt Arsenault2016-04-281-1/+3
| | | | | | | | The canonical form for allocas is a single allocation of the array type. In case we see a non-canonical array alloca, make sure we aren't replacing this with an array N times smaller. llvm-svn: 267916
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-283-0/+43
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [mips][atomics] Fix partword atomic binary operation implementationSimon Dardis2016-04-283-6/+15
| | | | | | | | | | | | | | | Currently Mips::emitAtomicBinaryPartword() does not properly respect the width of pointers. For MIPS64 this causes the memory address that the ll/sc sequence uses to be truncated. At runtime this causes a segmentation fault. This can be fixed by applying similar changes as r266204, so that a full 64bit pointer is loaded. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19651 llvm-svn: 267900
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-283-3/+42
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-281-1/+6
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [X86] Remove unused operand from a function and all its callers. NFCCraig Topper2016-04-285-10/+8
| | | | llvm-svn: 267854
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-2814-85/+10
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* [AArch64] Expand CTTZ for all vector types.Craig Topper2016-04-281-0/+9
| | | | llvm-svn: 267837
* [SystemZ] Support Swift Calling ConventionBryan Chan2016-04-284-3/+31
| | | | | | | | | | | | | | | | Summary: Port rL265480, rL264754, rL265997 and rL266252 to SystemZ, in order to enable the Swift port on the architecture. SwiftSelf and SwiftError are assigned to R10 and R9, respectively, which are normally callee-saved registers. For more information, see: RFC: Implementing the Swift calling convention in LLVM and Clang https://groups.google.com/forum/#!topic/llvm-dev/epDd2w93kZ0 Reviewers: kbarton, manmanren, rjmccall, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19414 llvm-svn: 267823
* [X86] Enable the post-RA-scheduler for clang's default 32-bit cpu.Mitch Bodart2016-04-272-12/+36
| | | | | | | | | For compilations with no explicit cpu specified, this exhibits nice gains on Silvermont, with neutral performance on big cores. Differential Revision: http://reviews.llvm.org/D19138 llvm-svn: 267809
* [X86][FastISel] Make sure we use the right register class when we select stores.Quentin Colombet2016-04-271-1/+9
| | | | llvm-svn: 267806
* [Hexagon] Merging nops in to previous packet rather than always creating a ↵Colin LeMahieu2016-04-271-17/+69
| | | | | | new one. llvm-svn: 267798
* [X86] Fix the lowering of TLS calls.Quentin Colombet2016-04-272-6/+9
| | | | | | | | | | | The callseq_end node must be glued with the TLS calls, otherwise, the generic code will miss the uses of the returned value and will mark it dead. Moreover, TLSCall 64-bit pseudo must not set an implicit-use on RDI, the pseudo uses the symbol address at this point not RDI and the lowering will do the right thing. llvm-svn: 267797
* AMDGPU: Account for globals in AMDGPUPromoteAlloca passMatt Arsenault2016-04-271-2/+4
| | | | | | Patch by Bas Nieuwenhuizen llvm-svn: 267791
* [ARM] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.Ahmed Bougacha2016-04-271-2/+2
| | | | | | | | | We run after PEI. Found via inspection; no obvious testcase. Follow-up to r266679. llvm-svn: 267781
* [AArch64] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.Ahmed Bougacha2016-04-271-2/+2
| | | | | | | | | We run after PEI. Found via inspection; no obvious testcase. Follow-up to r266339. llvm-svn: 267780
* [AArch64] Set correct successors in CMPXCHG pseudo expansion.Ahmed Bougacha2016-04-271-2/+4
| | | | | | | | | | | transferSuccessors() would LoadCmpBB a successor of DoneBB, whereas it should be a successor of the original MBB. Follow-up to r266339. Unfortunately, it's tricky to catch this in the verifier. llvm-svn: 267779
* [ARM] Set correct successors in CMPXCHG pseudo expansion.Ahmed Bougacha2016-04-271-2/+4
| | | | | | | | | | | | | | transferSuccessors() would LoadCmpBB a successor of DoneBB, whereas it should be a successor of the original MBB. The testcase changes are caused by Thumb2SizeReduction, which was previously confused by the broken CFG. Follow-up to r266679. Unfortunately, it's tricky to catch this in the verifier. llvm-svn: 267778
* [X86]: Quit promoting 16 bit loads to 32 bit.Kevin B. Smith2016-04-271-17/+0
| | | | | | Differential Revision: http://reviews.llvm.org/D19592 llvm-svn: 267773
* Add optimization bisect opt-in calls for PowerPC passesAndrew Kaylor2016-04-279-3/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D19554 llvm-svn: 267769
* [NVPTX] Run NVVMReflect at the beginning of IR passes.Justin Lebar2016-04-272-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently the NVVMReflect pass is run at the beginning of our backend passes. But really, it should be run as early as possible, as it's simply resolving an "if" statement in code. So copy it into TargetMachine::addEarlyAsPossiblePasses. We still run it at the beginning of the backend passes, since it's needed for correctness when lowering to nvptx. (Specifically, NVVMReflect changes each call to the __nvvm_reflect function or llvm.nvvm.reflect intrinsic into an integer constant, based on the pass's configuration. Clearly we miss many optimization opportunities if we perform this transformation at the beginning of codegen.) Reviewers: rnk Subscribers: tra, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D18616 llvm-svn: 267765
* Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for ↵Chad Rosier2016-04-276-39/+13
| | | | | | | | SMRD." This reverts commit r267733 due to a -Werror,-Wunused-function error. llvm-svn: 267752
* [DAGCombiner] Follow coding convention for function name (NFC)Gerolf Hoflehner2016-04-272-2/+2
| | | | llvm-svn: 267745
* [Mips] Add support for llvm.thread.pointer intrinsic.Marcin Koscielnicki2016-04-271-0/+4
| | | | | | | | This will be used to implement __builtin_thread_pointer in clang. Differential Revision: http://reviews.llvm.org/D19569 llvm-svn: 267743
* Silence a -Wdangling-elseReid Kleckner2016-04-271-1/+2
| | | | llvm-svn: 267737
* Add parentheses to silence buildbot warningMatthew Simpson2016-04-271-2/+2
| | | | llvm-svn: 267734
* [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.Artem Tamazov2016-04-276-13/+39
| | | | | | | | | | | Added support of TTMP quads. Reworked M0 exclusion machinery for SMRD and similar instructions to enable usage of TTMP registers in those instructions as destinations. Tests added. Differential Revision: http://reviews.llvm.org/D19342 llvm-svn: 267733
* AMDGPU/SI: Add llvm.amdgcn.s.waitcnt.all intrinsicNicolai Haehnle2016-04-272-14/+78
| | | | | | | | | | | | | | | | | Summary: So it appears that to guarantee some of the ordering requirements of a GLSL memoryBarrier() executed in the shader, we need to emit an s_waitcnt. (We can't use an s_barrier, because memoryBarrier() may appear anywhere in the shader, in particular it may appear in non-uniform control flow.) Reviewers: arsenm, mareko, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19203 llvm-svn: 267729
* [TTI] Add hook for vector extract with extensionMatthew Simpson2016-04-272-0/+58
| | | | | | | | | | | | | | | This change adds a new hook for estimating the cost of vector extracts followed by zero- and sign-extensions. The motivating example for this change is the SMOV and UMOV instructions on AArch64. These instructions move data from vector to general purpose registers while performing the corresponding extension (sign-extend for SMOV and zero-extend for UMOV) at the same time. For these operations, TargetTransformInfo can assume the extensions are free and only report the cost of the vector extract. The SLP vectorizer has been updated to make use of the new hook. Differential Revision: http://reviews.llvm.org/D18523 llvm-svn: 267725
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