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* [AVR] Don't worry about call frame size when initializing frame pointerDylan McKay2016-10-081-3/+2
| | | | | | | | | | | | | We previously only used the frame pointer if the frame pointer was too big. This was to work around a bug (described in this old commit) https://sourceforge.net/p/avr-llvm/code/204/tree//llvm/trunk/AVR/AVRFrameLowering.cpp?diff=50d64d912718465cb887d17a:203 I mistakenly invered the condition assuming it was a typo. I am now removing it because it doesn't seem to be a problem anymore (plus it's a dirty hack). llvm-svn: 283639
* [AVR] Don't shadow container while iterating in range-based loopDylan McKay2016-10-081-2/+4
| | | | | | This works on clang, but fails on GCC 4.6 llvm-svn: 283638
* [AVR] Use references rather than pointers in AVRISelLoweringDylan McKay2016-10-081-2/+2
| | | | llvm-svn: 283636
* Allow a maximum of 64 bits to be returned in registersDylan McKay2016-10-081-0/+8
| | | | | | | | The rest spills to the stack Authored by Jake Goulding llvm-svn: 283635
* [AVR] Expand MULHS for all typesDylan McKay2016-10-081-0/+3
| | | | | | | | | | Once MULHS was expanded, this exposed an issue where the condition register was thought to be 16-bit. This caused an attempt to copy a 16-bit register to an 8-bit register. Authored by Jake Goulding llvm-svn: 283634
* [AVR] Add the 'SoftFail' field to all instruction formatsDylan McKay2016-10-081-0/+2
| | | | | | This will be used in the future for disassembly. llvm-svn: 283630
* [AVR] Set up the instruction printer and the assembly backendDylan McKay2016-10-081-0/+19
| | | | llvm-svn: 283629
* [AVR] Add dependencies to AVR libraries in AVRCodeGenDylan McKay2016-10-081-1/+2
| | | | llvm-svn: 283628
* [AVR] Add missing subdirectories to LLVMBuildDylan McKay2016-10-081-1/+1
| | | | llvm-svn: 283627
* [AVR] Add the assembly printerDylan McKay2016-10-082-0/+183
| | | | | | | | | | | | Summary: This adds the AVRAsmPrinter class. Reviewers: arsenm, kparzysz Subscribers: llvm-commits, wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25271 llvm-svn: 283623
* AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizerTom Stellard2016-10-072-0/+23
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25250 llvm-svn: 283622
* AMDGPU/SI: Add support for 8-byte relocationsTom Stellard2016-10-071-0/+2
| | | | | | | | | | Reviewers: arsenm, kzhuravl Subscribers: wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25375 llvm-svn: 283593
* [Hexagon][NFC] Using documented instruction type name V4LDST instead of MEMOP.Colin LeMahieu2016-10-073-4/+4
| | | | llvm-svn: 283582
* AMDGPU/SI: Emit fixups for long branchesTom Stellard2016-10-071-0/+18
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25366 llvm-svn: 283570
* [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.Artem Tamazov2016-10-071-0/+10
| | | | | | | | | Partially fixes Bug 28232. Lit tests added. Differential Revision: https://reviews.llvm.org/D25367 llvm-svn: 283567
* [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx ↵Sam Kolton2016-10-078-54/+139
| | | | | | | | | | | | to AMDGPUBaseInfo.h Reviewers: artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D25084 llvm-svn: 283560
* [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';'Konstantin Zhuravlyov2016-10-071-1/+1
| | | | llvm-svn: 283558
* [AMDGPU] Promote uniform (i1, i16] operations to i32Konstantin Zhuravlyov2016-10-071-97/+101
| | | | | | Differential Revision: https://reviews.llvm.org/D25302 llvm-svn: 283555
* [ARM]: add missing switch case for cortex-r52Javed Absar2016-10-071-0/+1
| | | | | | | Adds a missing switch case for handling cortex-r52 in init-subtarget-features. llvm-svn: 283551
* [ARM] Reapply: Use __rt_div functions for divrem on WindowsMartin Storsjo2016-10-071-21/+45
| | | | | | | | | | | | | | | | | | | | | | | | Reapplying r283383 after revert in r283442. The additional fix is a getting rid of a stray space in a function name, in the refactoring part of the commit. This avoids falling back to calling out to the GCC rem functions (__moddi3, __umoddi3) when targeting Windows. The __rt_div functions have flipped the two arguments compared to the __aeabi_divmod functions. To match MSVC, we emit a check for division by zero before actually calling the library function (even if the library function itself also might do the same check). Not all calls to __rt_div functions for division are currently merged with calls to the same function with the same parameters for the remainder. This is more wasteful than a div + mls as before, but avoids calls to __moddi3. Differential Revision: https://reviews.llvm.org/D25332 llvm-svn: 283550
* [ARM]: Add Cortex-R52 target to LLVMJaved Absar2016-10-073-4/+24
| | | | | | | This patch adds Cortex-R52, the new ARM real-time processor, to LLVM. Cortex-R52 implements the ARMv8-R architecture. llvm-svn: 283542
* [X86][SSE] Update register class during MOVSD/MOVSS - BLENDPD/BLENDPS ↵Simon Pilgrim2016-10-071-0/+11
| | | | | | | | | | | | | | commutation MOVSD/MOVSS take a 128-bit register and a FR32/FR64 register input, the commutation code wasn't taking this into account leading to verification errors. This patch inserts a vreg copy mi to ensure that the registers are correct. Fix for PR30607 Differential Revision: https://reviews.llvm.org/D25280 llvm-svn: 283539
* [ARM] Don't convert switches to lookup tables of pointers with ROPI/RWPIOliver Stannard2016-10-071-0/+10
| | | | | | | | | | | | With the ROPI and RWPI relocation models we can't always have pointers to global data or functions in constant data, so don't try to convert switches into lookup tables if any value in the lookup table would require a relocation. We can still safely emit lookup tables of other values, such as simple constants. Differential Revision: https://reviews.llvm.org/D24462 llvm-svn: 283530
* Use StringRef in ARMELFStreamer (NFC)Mehdi Amini2016-10-071-2/+2
| | | | llvm-svn: 283529
* AMDGPU: Fix use-after-free in SIOptimizeExecMaskingNicolai Haehnle2016-10-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There was a bug with sequences like s_mov_b64 s[0:1], exec s_and_b64 s[2:3]<def>, s[0:1], s[2:3]<kill> ... s_mov_b64_term exec, s[2:3] because s[2:3] was defined and used in the same instruction, ending up with SaveExecInst inside OtherUseInsts. Note that the test case also exposes an unrelated bug. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98028 Reviewers: tstellarAMD, arsenm Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25306 llvm-svn: 283528
* Use StringReg in TargetParser APIs (NFC)Mehdi Amini2016-10-072-2/+2
| | | | llvm-svn: 283527
* Revert "Revert "Add a static_assert to enforce that parameters to ↵Mehdi Amini2016-10-071-1/+2
| | | | | | | | | llvm::format() are not totally unsafe"" This reverts commit r283510 and reapply r283509, with updates to clang-tools-extra as well. llvm-svn: 283525
* [X86] Fix patterns for VPMULLD and VPCMPEQQ to not require aligned loads.Craig Topper2016-10-071-2/+2
| | | | llvm-svn: 283524
* [X86] Remove unused PatFrags. NFCCraig Topper2016-10-071-5/+0
| | | | llvm-svn: 283523
* [AVR] Add the AVRMCInstLower classDylan McKay2016-10-073-0/+144
| | | | | | | | | | | | | | Summary: This class deals with the lowering of CodeGen `MachineInstr` objects to MC `MCInst` objects. Reviewers: kparzysz, arsenm Subscribers: wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25269 llvm-svn: 283522
* Target: Remove unused patterns and transforms. NFC.Peter Collingbourne2016-10-0713-203/+0
| | | | llvm-svn: 283515
* [Hexagon] NFC Removing 'V4_' prefix from duplex instruction names.Colin LeMahieu2016-10-074-471/+471
| | | | llvm-svn: 283514
* Revert "Add a static_assert to enforce that parameters to llvm::format() are ↵Mehdi Amini2016-10-061-2/+1
| | | | | | | | not totally unsafe" This reverts commit r283509, clang is hitting the assert. llvm-svn: 283510
* Add a static_assert to enforce that parameters to llvm::format() are not ↵Mehdi Amini2016-10-061-1/+2
| | | | | | | | | | | | | | | | | | | | | totally unsafe Summary: I had for the second time today a bug where llvm::format("%s", Str) was called with Str being a StringRef. The Linux and MacOS bots were fine, but windows having different calling convention, it printed garbage. Instead we can catch this at compile-time: it is never expected to call a C vararg printf-like function with non scalar type I believe. Reviewers: bogner, Bigcheese, dexonsmith Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25266 llvm-svn: 283509
* [Hexagon] NFC. Canonicalizing absolute address instruction names.Colin LeMahieu2016-10-064-125/+125
| | | | llvm-svn: 283507
* [WebAssemby] Implement block signatures.Dan Gohman2016-10-0612-61/+199
| | | | | | | | | Per spec changes, this implements block signatures, and adds just enough logic to produce correct block signatures at the ends of functions. Differential Revision: https://reviews.llvm.org/D25144 llvm-svn: 283503
* [WebAssembly] Remove loop's bottom label.Dan Gohman2016-10-062-26/+16
| | | | | | | | Per spec changes, loop constructs no longer have a bottom label. https://reviews.llvm.org/D25118 llvm-svn: 283502
* [WebAssembly] Remove the output operand from stores.Dan Gohman2016-10-067-88/+64
| | | | | | | | | Per spec changes, store instructions in WebAssembly no longer have a return value. Update the instruction descriptions. Differential Revision: https://reviews.llvm.org/D25122 llvm-svn: 283501
* [X86] Preserve BasePtr for LEA64_32rMichael Kuperstein2016-10-061-3/+5
| | | | | | | | | | | | When replacing FrameIndex with BasePtr, we must preserve BasePtr for LEA64_32r since BasePtr is used later for stack adjustment if it is the same as StackPtr. Patch by H.J Lu <hjl.tools@gmail.com> Differential Revision: https://reviews.llvm.org/D23575 llvm-svn: 283486
* AMDGPU: Don't fold undef uses or copies with implicit usesMatt Arsenault2016-10-061-4/+22
| | | | llvm-svn: 283476
* AMDGPU: Remove scheduling info from si_mask_branchMatt Arsenault2016-10-061-0/+2
| | | | llvm-svn: 283475
* AMDGPU: Remove leftover implicit operands when folding immediatesMatt Arsenault2016-10-061-7/+26
| | | | | | | | When constant folding an operation to a copy or an immediate mov, the implicit uses/defs of the old instruction were left behind, e.g. replacing v_or_b32 left the implicit exec use on the new copy. llvm-svn: 283471
* Reapply "AMDGPU: Support using tablegened MC pseudo expansions"Matt Arsenault2016-10-065-44/+75
| | | | | | Fix bad merge llvm-svn: 283470
* Revert "AMDGPU: Support using tablegened MC pseudo expansions"Matt Arsenault2016-10-065-68/+44
| | | | llvm-svn: 283469
* AMDGPU: Support using tablegened MC pseudo expansionsMatt Arsenault2016-10-065-44/+68
| | | | | | Make the necessary refactorings to make use of PseudoInstExpansion llvm-svn: 283467
* BranchRelaxation: Support expanding unconditional branchesMatt Arsenault2016-10-069-17/+271
| | | | | | | AMDGPU needs to expand unconditional branches in a new block with an indirect branch. llvm-svn: 283464
* [Hexagon] Avoid replacing full regs with subregisters in tied operandsKrzysztof Parzyszek2016-10-061-0/+20
| | | | | | Doing so will result in the two-address pass generating incorrect code. llvm-svn: 283463
* Move AArch64BranchRelaxation to generic codeMatt Arsenault2016-10-064-421/+2
| | | | llvm-svn: 283459
* AArch64: Move remaining target specific BranchRelaxation bits to TIIMatt Arsenault2016-10-063-53/+37
| | | | llvm-svn: 283458
* [X86] Fix intel syntax push parsing bugNirav Dave2016-10-061-2/+29
| | | | | | | | | | | | | | | Change erroneous parsing of push immediate instructions in intel syntax to default to pointer size by rewriting into the ATT style for matching. This fixes PR22028. Reviewers: majnemer, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25288 llvm-svn: 283457
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