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* ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.Jim Grosbach2011-09-011-1/+1
| | | | llvm-svn: 138952
* Fix vbroadcast matching logic to early unmatch if the node doesn't haveBruno Cardoso Lopes2011-09-011-1/+5
| | | | | | only one use. Fix PR10825. llvm-svn: 138951
* Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy2011-09-011-593/+595
| | | | llvm-svn: 138948
* t2Bcc is allowed to have a predicate without a preceding IT instruction.Owen Anderson2011-09-011-1/+2
| | | | llvm-svn: 138946
* Thumb2 assembly parsing and encoding for ADD(immediate).Jim Grosbach2011-09-012-6/+50
| | | | llvm-svn: 138922
* Fixup for functions that return a bool.Chad Rosier2011-08-311-2/+2
| | | | llvm-svn: 138918
* Static relocation model Thumb jump table interworking.Jim Grosbach2011-08-311-0/+5
| | | | | | | Make sure the low bit of the PC is set when loading an address directly for jump tables in static relocation model. llvm-svn: 138912
* The asm parser currently selects the wrong encoding for non-conditional ↵Owen Anderson2011-08-312-5/+6
| | | | | | Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. llvm-svn: 138910
* Thumb2 t2Bcc should encode as t2B when condition is 'always'.Jim Grosbach2011-08-311-0/+5
| | | | llvm-svn: 138898
* Move more code around and duplicate AVX patterns: MOVHPS and MOVLPSBruno Cardoso Lopes2011-08-311-109/+216
| | | | llvm-svn: 138897
* Move MOVAPS,MOVUPS patterns close to the instructions definitionBruno Cardoso Lopes2011-08-311-88/+92
| | | | llvm-svn: 138896
* Remove "_Int" forms of MOVUPSmr and MOVAPSmrBruno Cardoso Lopes2011-08-311-16/+13
| | | | llvm-svn: 138895
* Fix encoding for tBcc with immediate offset operand.Owen Anderson2011-08-311-1/+5
| | | | llvm-svn: 138889
* When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still ↵Owen Anderson2011-08-311-1/+8
| | | | | | | | need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. <rdar://problem/10046188> llvm-svn: 138885
* Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.Jim Grosbach2011-08-311-3/+1
| | | | | | | | When we want encoding T3 (the wide encoding), we can explicitly check for that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly handle encodings T1 and T2 when in Thumb2 mode. llvm-svn: 138879
* Fix roundtripping of Thumb BL/BLX instructions with immediate offsets ↵Owen Anderson2011-08-311-3/+31
| | | | | | instead of labels. llvm-svn: 138874
* tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).Jim Grosbach2011-08-311-2/+2
| | | | llvm-svn: 138873
* Thumb2 parsing and encoding for ADC(register).Jim Grosbach2011-08-311-1/+22
| | | | | | | Also add instruction aliases for non-.w versions of SBC since they're the same. llvm-svn: 138871
* 64-bit atomic cmpxchg for ARM.Eli Friedman2011-08-314-37/+93
| | | | llvm-svn: 138868
* Fix typo. Patch by Liu.Akira Hatanaka2011-08-311-1/+1
| | | | llvm-svn: 138866
* Tweak Thumb1 ADD encoding selection a bit.Jim Grosbach2011-08-311-2/+5
| | | | | | | | When the destination register of an add immediate instruction is explicitly specified, encoding T1 is preferred, else encoding T2 is preferred. llvm-svn: 138862
* Put VMOVS widening under a command line option, off by default.Jakob Stoklund Olesen2011-08-311-1/+6
| | | | | | | | | | | It appears that our use of the imp-use and imp-def flags with sub-registers is not yet robust enough to support this. The failing test case is complicated, I am working on a reduction. <rdar://problem/10044201> llvm-svn: 138861
* Spelling and grammar fixes to problems found by Duncan.Rafael Espindola2011-08-311-2/+2
| | | | llvm-svn: 138858
* Make sure we don't crash when -miphoneos-version-min is specified on x86. ↵Eli Friedman2011-08-311-1/+2
| | | | | | Hopefully this will fix gcc testsuite failures. llvm-svn: 138856
* Rework this conditional a bit.Eric Christopher2011-08-311-6/+10
| | | | | | Patch by Sanjoy Das llvm-svn: 138853
* - Move all MOVSS and MOVSD patterns close to their definitionsBruno Cardoso Lopes2011-08-312-144/+239
| | | | | | | | - Duplicate some store patterns to their AVX forms! - Catched a bug while restricting the patterns subtarget, fix it and update a testcase to check it properly llvm-svn: 138851
* Remove unnecessary AVX checksBruno Cardoso Lopes2011-08-311-3/+3
| | | | llvm-svn: 138850
* Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,Bruno Cardoso Lopes2011-08-312-6/+16
| | | | | | whenever AVX is enabled. llvm-svn: 138849
* Fix (movhps load) lowering / pattern to match more cases. rdar://10050549Evan Cheng2011-08-312-3/+7
| | | | llvm-svn: 138848
* Some minor cleanups for r138845.Eli Friedman2011-08-311-22/+0
| | | | llvm-svn: 138846
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-314-1/+277
| | | | llvm-svn: 138845
* Fix issues with disassembly of IT instructions involving condition codes ↵Owen Anderson2011-08-302-30/+32
| | | | | | other the EQ/NE. Discovered by roundtrip testing. llvm-svn: 138840
* Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather ↵Owen Anderson2011-08-301-1/+4
| | | | | | than labels. llvm-svn: 138837
* Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets ↵Owen Anderson2011-08-301-1/+4
| | | | | | instead of labels. llvm-svn: 138835
* Fix encoding of Thumb1 B instructions with immediate offsets, which is ↵Owen Anderson2011-08-301-1/+4
| | | | | | necessary for round-tripping. llvm-svn: 138834
* Clean up whitespace.Owen Anderson2011-08-301-8/+8
| | | | llvm-svn: 138833
* Fix off-by-one error Benjamin noticed.Bill Wendling2011-08-301-1/+1
| | | | llvm-svn: 138832
* Enable compact unwind info by default. This only applies to Darwin when CFI isBill Wendling2011-08-301-9/+1
| | | | | | disabled. llvm-svn: 138826
* Fix C++0x narrowing errors when char is unsigned.Jeffrey Yasskin2011-08-301-2/+2
| | | | | | | In the case of EDInstInfo, this would actually cause a bug when -1 became 255 and was then compared >=0 in llvm-mc/Disassembler.cpp. llvm-svn: 138825
* Adds support for variable sized allocas. For a variable sized alloca,Rafael Espindola2011-08-302-15/+166
| | | | | | | | | | | | code is inserted to first check if the current stacklet has enough space. If so, space is allocated by simply decrementing the stack pointer. Otherwise a runtime routine (__morestack_allocate_stack_space in libgcc) is called which allocates the required memory from the heap. Patch by Sanjoy Das. llvm-svn: 138818
* Adds a SelectionDAG node X86SegAlloca which will be custom loweredRafael Espindola2011-08-304-0/+31
| | | | | | | | | | | | from DYNAMIC_STACKALLOC. Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which will match X86SegAlloca (based on word size) are also added. They will be custom emitted to inject the actual stack handling code. Patch by Sanjoy Das. llvm-svn: 138814
* Emit segmented-stack specific code into function prologues forRafael Espindola2011-08-304-3/+174
| | | | | | | | | | | | X86. Modify the pass added in the previous patch to call this new code. This new prologues generated will call a libgcc routine (__morestack) to allocate more stack space from the heap when required Patch by Sanjoy Das. llvm-svn: 138812
* Command line option to enable support for segmented stacks:Rafael Espindola2011-08-301-0/+7
| | | | | | | -segmented-stacks. Patch by Sanjoy Das! llvm-svn: 138811
* Follow up to r138791.Evan Cheng2011-08-304-2/+30
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Set CR1EQ only when lowering vararg floating arguments (not any varargRoman Divacky2011-08-302-2/+10
| | | | | | arguments as before), unset CR1EQ otherwise. llvm-svn: 138802
* Fix typos in SPUMCTargetDesc.hJames Molloy2011-08-301-2/+2
| | | | | | Patch supplied by Liu (projlc@gmail.com) llvm-svn: 138799
* Fix typo in BlackfinFrameLowering.hJames Molloy2011-08-301-2/+2
| | | | | | Patch supplied by Liu (projlc@gmail.com) llvm-svn: 138798
* Fix typo in MSP430MCTargetDesc.h.James Molloy2011-08-301-2/+2
| | | | | | Patch supplied by Liu (projlc@gmail.com) llvm-svn: 138797
* Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com)James Molloy2011-08-301-4/+4
| | | | llvm-svn: 138796
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-307-346/+358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
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