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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-08-31 17:00:02 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-08-31 17:00:02 +0000 |
| commit | cd893390f5e27f1a3745e2af872d29ad7d226272 (patch) | |
| tree | b12fa0c90a12a8e3afcfc40ea07d8499b61fb5df /llvm/lib/Target | |
| parent | 4aa01ef19c4d8484ac2364761fdc68fbf1bf7712 (diff) | |
| download | bcm5719-llvm-cd893390f5e27f1a3745e2af872d29ad7d226272.tar.gz bcm5719-llvm-cd893390f5e27f1a3745e2af872d29ad7d226272.zip | |
Put VMOVS widening under a command line option, off by default.
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
llvm-svn: 138861
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 0e2915fedd2..f8096b98c59 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -46,6 +46,10 @@ static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")); +static cl::opt<bool> +WidenVMOVS("widen-vmovs", cl::Hidden, + cl::desc("Widen ARM vmovs to vmovd when possible")); + /// ARM_MLxEntry - Record information about MLA / MLS instructions. struct ARM_MLxEntry { unsigned MLxOpc; // MLA / MLS opcode @@ -637,7 +641,8 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, // a VMOVD since that can be converted to a NEON-domain move by // NEONMoveFix.cpp. Check that MI is the original COPY instruction, and // that it really defines the whole D-register. - if ((DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 && + if (WidenVMOVS && + (DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 && I != MBB.end() && I->isCopy() && I->getOperand(0).getReg() == DestReg && I->getOperand(1).getReg() == SrcReg) { |
