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* [AVX] Insert/extract subvector lowering support. This includes aDavid Greene2011-02-071-2/+101
| | | | | | | couple of utility functions that will be used in other places for more AVX lowering. llvm-svn: 125029
* ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .oJason W Kim2011-02-071-3/+3
| | | | llvm-svn: 125025
* Fix an obvious typo which caused an isel assertion. rdar://8964854.Evan Cheng2011-02-071-1/+1
| | | | llvm-svn: 125023
* Add codegen support for using post-increment NEON load/store instructions.Bob Wilson2011-02-073-145/+546
| | | | | | | | The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
* Change VLD3/4 and VST3/4 for quad registers to not update the address register.Bob Wilson2011-02-073-65/+89
| | | | | | | | | | | | These operations are expanded to pairs of loads or stores, and the first one uses the address register update to produce the address for the second one. So far, the second load/store has also updated the address register, just for convenience, since that output has never been used. In anticipation of actually supporting post-increment updates for these operations, this changes the non-updating operations to use a non-updating load/store for the second instruction. llvm-svn: 125013
* Fix some NEON instruction itineraries.Bob Wilson2011-02-071-12/+16
| | | | llvm-svn: 125012
* Fix a comment: addrmode6 no longer includes the optional writeback flag.Bob Wilson2011-02-071-1/+1
| | | | llvm-svn: 125011
* Remove inaccurate comments: so_imm and t2_so_imm operands are not encodedBob Wilson2011-02-072-8/+2
| | | | | | until the instructions are emitted or printed. llvm-svn: 125010
* Move code for OffsetCompare struct closer to where it is used.Bob Wilson2011-02-071-11/+11
| | | | llvm-svn: 125009
* Rework some .ARM.attribute work for improved gcc compatibility.Jason W Kim2011-02-072-13/+84
| | | | | | | Unified EmitTextAttribute for both Asm and Obj emission (.cpu only) Added necessary cortex-A8 related attrs for codegen compat tests. llvm-svn: 124995
* Remove a virtual inheritance case that clang can devirtualize fully now.Anders Carlsson2011-02-061-21/+0
| | | | llvm-svn: 124989
* Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be ↵NAKAMURA Takumi2011-02-053-9/+20
| | | | | | enough for caller to allocate one. llvm-svn: 124949
* lib/Target/X86/X86ISelLowering.cpp: Introduce a new variable "IsWin64". No ↵NAKAMURA Takumi2011-02-051-3/+4
| | | | | | functional changes. llvm-svn: 124948
* lib/Target/X86/X86JITInfo.cpp: Add Win64 stuff.NAKAMURA Takumi2011-02-051-0/+8
| | | | llvm-svn: 124947
* Target/X86: Fix whitespace.NAKAMURA Takumi2011-02-053-7/+7
| | | | llvm-svn: 124946
* [AVX] Revert 124910 until clients are ready.David Greene2011-02-051-122/+0
| | | | llvm-svn: 124912
* [AVX] Add some utilities to insert and extract 128-bit subvectors.David Greene2011-02-041-0/+122
| | | | | | | | This allows us to easily support 256-bit operations that don't have native 256-bit support. This applies to integer operations, certain types of shuffles and various othher things. llvm-svn: 124910
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-045-10/+70
| | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
* MC/AsmParser: Add support for allowing the conversion process to fail (viaDaniel Dunbar2011-02-043-0/+6
| | | | | | custom conversion functions). llvm-svn: 124872
* [AVX] Support VSINSERTF128 with more patterns and appropriateDavid Greene2011-02-044-0/+77
| | | | | | | infrastructure. This makes lowering 256-bit vectors to 128-bit vectors simple when 256-bit vector support is not available. llvm-svn: 124868
* Fix 80-column violations and whitespace.Bob Wilson2011-02-032-4/+5
| | | | llvm-svn: 124819
* [AVX] VEXTRACTF128 support. This commit includes patterns forDavid Greene2011-02-034-0/+76
| | | | | | | | | | matching EXTRACT_SUBVECTOR to VEXTRACTF128 along with support routines to examine and translate index values. VINSERTF128 comes next. With these two in place we can begin supporting more AVX operations as INSERT/EXTRACT can be used as a fallback when 256-bit support is not available. llvm-svn: 124797
* Add XCore intrinsics for resource instructions.Richard Osborne2011-02-031-4/+51
| | | | llvm-svn: 124794
* Fix PR9127 by reversing the operands even if they have more then one use.Rafael Espindola2011-02-031-2/+2
| | | | | | | | Reversing the operands allows us to fold, but doesn't force us to. Also, at this point the DAG is still being optimized, so the check for hasOneUse is not very precise. llvm-svn: 124773
* Update comment to match my recent change.Bob Wilson2011-02-021-2/+2
| | | | llvm-svn: 124725
* SimplifyCFG: Turn switches into sub+icmp+branch if possible.Benjamin Kramer2011-02-021-48/+0
| | | | | | | | | | | | | | | | | This makes the job of the later optzn passes easier, allowing the vast amount of icmp transforms to chew on it. We transform 840 switches in gcc.c, leading to a 16k byte shrink of the resulting binary on i386-linux. The testcase from README.txt now compiles into decl %edi cmpl $3, %edi sbbl %eax, %eax andl $1, %eax ret llvm-svn: 124724
* Add support for trampolines on the XCore.Richard Osborne2011-02-024-1/+72
| | | | llvm-svn: 124722
* Fixed a bug in the disassembler where the mandatory 0x66Sean Callanan2011-02-021-0/+1
| | | | | | | | prefix would be misinterpreted in some cases on 32-bit x86 platforms. Thanks to Olivier Meurant for identifying the bug. llvm-svn: 124709
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-022-2/+9
| | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 llvm-svn: 124708
* PR9081: Split up LDM instruction with deprecated use of both LR and PC.Bob Wilson2011-02-011-2/+3
| | | | | | | This is completely untested but pretty straightforward, so hopefully I got it right. llvm-svn: 124694
* Fix imm printing for logical instructions.Anton Korobeynikov2011-02-013-24/+45
| | | | | | Patch by Brian G. Lucas! llvm-svn: 124679
* Test commit - fix a double 'should' in a comment.Carl Norum2011-02-011-1/+1
| | | | llvm-svn: 124652
* Patches to build EFI with Clang/LLVM. By Carl Norum.Evan Cheng2011-02-016-16/+36
| | | | llvm-svn: 124639
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-316-25/+25
| | | | llvm-svn: 124611
* Fix vector sign extend to put the source and destination types in theDavid Greene2011-01-311-3/+3
| | | | | | correct places. llvm-svn: 124601
* add a note, progress unblocked by PR8575 being fixed.Chris Lattner2011-01-311-0/+48
| | | | llvm-svn: 124599
* Save a mapping between original and cloned constpool entries.Anton Korobeynikov2011-01-302-0/+25
| | | | llvm-svn: 124570
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-21/+0
| | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
* PR9030: Fix disassembly of ARM "mov pc, lr" instruction.Bob Wilson2011-01-281-2/+2
| | | | | | Patch by Jyun-Yan You. llvm-svn: 124492
* Fix PLD encoding.Evan Cheng2011-01-271-2/+2
| | | | llvm-svn: 124458
* Changed llvm-mc arm target to give an error if .syntax divided is used. SinceKevin Enderby2011-01-271-1/+1
| | | | | | only .syntax unified is supported. llvm-svn: 124454
* [AVX] Clean up the code to configure target lowering for AVX. SpecifyDavid Greene2011-01-271-73/+47
| | | | | | | how to lower more/new operations. This is a prerequisite for adding additional AVX lowering. llvm-svn: 124447
* Introduce virtual ParseRegister method in TargetAsmParser.Roman Divacky2011-01-273-6/+19
| | | | | | Create override of this method in X86/ARM/MBlaze. llvm-svn: 124378
* Use the incoming VT not the VT of where we're trying to store to determineEric Christopher2011-01-271-2/+2
| | | | | | | | if we can store a value. Also, the exclusion is or, not and. Fixes rdar://8920247. llvm-svn: 124357
* lib/Target/X86/X86ISelDAGToDAG.cpp: __main should be WINCALL64 on Win64.NAKAMURA Takumi2011-01-271-1/+1
| | | | | | CALL64 marks %xmm* as dead. llvm-svn: 124354
* Add support for printing out floating point values from the ARM assemblyBill Wendling2011-01-261-2/+27
| | | | | | | parser. The parser will always give us a binary representation of the floating point number. llvm-svn: 124318
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-262-1/+23
| | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. llvm-svn: 124307
* [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene2011-01-262-0/+13
| | | | | | | | implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. llvm-svn: 124292
* fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructionsBruno Cardoso Lopes2011-01-261-0/+1
| | | | llvm-svn: 124288
* Add needed braces.Bill Wendling2011-01-261-1/+2
| | | | llvm-svn: 124273
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