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* [X86] Call getScalarSizeInBits() instead of ↵Craig Topper2015-10-311-5/+5
| | | | | | getScalarType().getScalarSizeInBits(). NFC llvm-svn: 251744
* [X86] Remove two const references to the return value of a constructor and ↵Craig Topper2015-10-311-2/+2
| | | | | | just use normal object creation syntax. NFC llvm-svn: 251743
* [X86] Replace EVT with MVT in some more places. NFCCraig Topper2015-10-311-12/+12
| | | | llvm-svn: 251742
* [X86] Fix indentation of case statements in switch. NFCCraig Topper2015-10-311-16/+16
| | | | llvm-svn: 251741
* [X86] Reduce math for index calculation for inserting and extracting ↵Craig Topper2015-10-311-14/+16
| | | | | | subvectors and elements by exploiting the fact that all supported vector types have a power 2 number of elements. llvm-svn: 251740
* [WebAssembly] Fix import statementJF Bastien2015-10-301-9/+10
| | | | | | | | | | Summary: Imports should be generated like (param i32 f32...) not (param i32) (param f32) ... Author: binji Reviewers: jfb Subscribers: jfb, dschuff llvm-svn: 251714
* [X86] Use is128BitVector/is256BitVector/is512BitVector in place of ↵Craig Topper2015-10-301-17/+16
| | | | | | getSizeInBits == in some places. NFC llvm-svn: 251687
* [X86] Minor formatting fixes. NFC.Craig Topper2015-10-301-9/+8
| | | | llvm-svn: 251686
* [X86] Use MVT instead of EVT in some places. NFCCraig Topper2015-10-301-37/+41
| | | | | | Prior to this the compiled code probably had extra checks for extended types that won't ever execute. llvm-svn: 251682
* [X86][SSE] Shuffle blends with zeroSimon Pilgrim2015-10-291-19/+49
| | | | | | | | This patch generalizes the zeroing of vector elements with the BLEND instructions. Currently a zero vector will only blend if the shuffled elements are correctly inline, this patch recognises when a vector input is zero (or zeroable) and modifies a local copy of the shuffle mask to support a blend. As a zeroable vector input may not be all zeroes, the zeroable vector is regenerated if necessary. Differential Revision: http://reviews.llvm.org/D14050 llvm-svn: 251659
* [SystemZ] Make the CCRegs regclass non-allocatable.Jonas Paulsson2015-10-293-4/+6
| | | | | | | | | | | | | | | | | | | | | This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
* AMDGPU/SI: handle undef for llvm.SI.packf16Marek Olsak2015-10-291-0/+4
| | | | llvm-svn: 251632
* AMDGPU/SI: use S_OR for fneg (fabs f32)Marek Olsak2015-10-291-2/+1
| | | | llvm-svn: 251631
* AMDGPU/SI: use S_AND for i1 truncMarek Olsak2015-10-291-2/+2
| | | | llvm-svn: 251630
* [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is usedZoran Jovanovic2015-10-291-5/+10
| | | | | | | | | | | | | | | Summary: This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary. Author: Jelena.Losic Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13593 llvm-svn: 251629
* Recognize that ARM1176JZ[F]-S support TrustZoneArtyom Skrobov2015-10-292-1/+4
| | | | | | | | | | | | | | Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
* [mips] Check the register class before replacing materializations of zero ↵Vasileios Kalintiris2015-10-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | with $zero in microMIPS. Summary: The microMIPS register class GPRMM16 does not contain the $zero register. However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses of the $dst register: [d]addiu, $dst, $zero, 0 with the $zero register, without checking for membership in the register class of the target machine operand. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13984 llvm-svn: 251622
* [WebAssembly] Update opcode name format for conversionsJF Bastien2015-10-292-27/+35
| | | | | | | | | | | | Summary: Conversion opcode name format should be f64.convert_u/i64 not f64_convert_u Author: s3ththompson Reviewers: jfb Subscribers: sunfish, jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14160 llvm-svn: 251613
* Remove CRLF line endings.Benjamin Kramer2015-10-291-6/+6
| | | | llvm-svn: 251594
* [PowerPC] Recurse through constants when looking for TLS globalsHal Finkel2015-10-281-2/+10
| | | | | | | | | | | | | We cannot form ctr-based loops around function calls, including calls to __tls_get_addr used for PIC TLS variables. References to such TLS variables, however, might be buried within constant expressions, and so we need to search the entire constant expression to be sure that no references to such TLS variables exist. Fixes PR25256, reported by Eric Schweitz. This is a slightly-modified version of the patch suggested by Eric in the bug report, and a test case I created. llvm-svn: 251582
* [PowerPC] Don't return unsupported register classes for asm constraintsHal Finkel2015-10-281-5/+6
| | | | | | | | | As a follow-up to r251566, do the same for the other optionally-supported register classes (mostly for vector registers). Don't return an unavailable register class (which would cause an assert later), but fail cleanly when provided an unsupported inline asm constraint. llvm-svn: 251575
* ARM: add support for WatchOS's compact unwind information.Tim Northover2015-10-286-9/+240
| | | | llvm-svn: 251573
* ARM: teach backend about WatchOS and TvOS libcalls.Tim Northover2015-10-282-24/+48
| | | | | | | The most substantial changes are again for watchOS: libcalls are hard-float if needed and sincos has a different calling convention. llvm-svn: 251571
* ARM: add backend support for the ABI used in WatchOSTim Northover2015-10-288-16/+42
| | | | | | | At the LLVM level this ABI is essentially a minimal modification of AAPCS to support 16-byte alignment for vector types and the stack. llvm-svn: 251570
* ARM: support .watchos_version_min and .tvos_version_min.Tim Northover2015-10-281-1/+9
| | | | | | | | These MachO file directives are used by linkers and other tools to provide compatibility information, much like the existing .ios_version_min and .macosx_version_min. llvm-svn: 251569
* [PowerPC] Cleanly reject asm crbit constraint with -crbitsHal Finkel2015-10-281-1/+2
| | | | | | | When crbits are disabled, cleanly reject the constraint (return the register class only to cause an assert later). llvm-svn: 251566
* [X86] A small fix in X86/X86TargetTransformInfo.cpp: check a value type is ↵Cong Hou2015-10-281-1/+2
| | | | | | simple before calling getSimpleVT(). llvm-svn: 251538
* [ARM] Allow SP in rGPR, starting from ARMv8Artyom Skrobov2015-10-282-13/+36
| | | | | | | | | | | | | | | | | Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
* Put global classes into the appropriate namespace.Benjamin Kramer2015-10-284-6/+9
| | | | | | | Most of the cases belong into an anonymous namespace. No functionality change intended. llvm-svn: 251515
* [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI ↵Hrvoje Varga2015-10-286-7/+158
| | | | | | | | and WAIT instructions Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
* [X86] Make some for loops over MVTs more explicit (and shorter) by just ↵Craig Topper2015-10-281-42/+7
| | | | | | mentioning all the relevant types in an initializer list. NFC llvm-svn: 251500
* Use range-based for loops and use initializer list to remove a small static ↵Craig Topper2015-10-281-7/+5
| | | | | | array. NFC llvm-svn: 251494
* Remove templates from CostTableLookup functions. All instantiations had the ↵Craig Topper2015-10-283-46/+36
| | | | | | | | same type. This also lets us remove the versions of the functions that took a statically sized array as we can rely on ArrayRef implicit conversion now. llvm-svn: 251490
* [PowerPC] Replace cntlz[.] with cntlzw[.]Hal Finkel2015-10-281-2/+5
| | | | | | | | | | | | | | | | | | | cntlz is the old POWER mnemonic. cntlzw is the PowerPC mnemonic. This change fixes an issue when -no-integrated-as: The opcode cntlz is unrecognized by gas Alias the POWER mnemonic cntlz[.] to the PowerPC mnemonic cntlzw[.] This is done for because the POWER cntlz mnemonic has be used by LLVM for a very long time. We need to make sure that assembly programs that are using the cntlz[.] do not break with this change. Change PowerPC tests to reflect the insn change from cntlz to cntlzw. Add assembly test to verify cntlz[.] is encoded correctly. Patch by Tom Rix! llvm-svn: 251489
* [AArch64]Merge halfword loads into a 32-bit loadJun Bum Lim2015-10-271-45/+216
| | | | | | | | | | | | | | | | This recommits r250719, which caused a failure in SPEC2000.gcc because of the incorrect insert point for the new wider load. Convert two halfword loads into a single 32-bit word load with bitfield extract instructions. For example : ldrh w0, [x2] ldrh w1, [x2, #2] becomes ldr w0, [x2] ubfx w1, w0, #16, #16 and w0, w0, #ffff llvm-svn: 251438
* Create a new interface addSuccessorWithoutWeight(MBB*) in MBB to add ↵Cong Hou2015-10-271-5/+6
| | | | | | | | | | | | | | successors when optimization is disabled. When optimization is disabled, edge weights that are stored in MBB won't be used so that we don't have to store them. Currently, this is done by adding successors with default weight 0, and if all successors have default weights, the weight list will be empty. But that the weight list is empty doesn't mean disabled optimization (as is stated several times in MachineBasicBlock.cpp): it may also mean all successors just have default weights. We should discourage using default weights when adding successors, because it is very easy for users to forget update the correct edge weights instead of using default ones (one exception is that the MBB only has one successor). In order to detect such usages, it is better to differentiate using default weights from the case when optimizations is disabled. In this patch, a new interface addSuccessorWithoutWeight(MBB*) is created for when optimization is disabled. In this case, MBB will try to maintain an empty weight list, but it cannot guarantee this as for many uses of addSuccessor() whether optimization is disabled or not is not checked. But it can guarantee that if optimization is enabled, then the weight list always has the same size of the successor list. Differential revision: http://reviews.llvm.org/D13963 llvm-svn: 251429
* [X86][AVX512] [X86][AVX512] add convert float to halfAsaf Badouh2015-10-273-21/+52
| | | | | | | | convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem). Differential Revision: http://reviews.llvm.org/D14113 llvm-svn: 251409
* [ARM] Expand ROTL and ROTR of vector value typesCharlie Turner2015-10-272-1/+9
| | | | | | | | | | | | Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection. Reviewers: rengolin, t.p.northover Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14082 llvm-svn: 251401
* [X86] Make elfiamcu an OS, not an environment.Michael Kuperstein2015-10-271-1/+1
| | | | | | | | | | GNU tools require elfiamcu to take up the entire OS field, so, e.g. i?86-*-linux-elfiamcu is not considered a legal triple. Make us compatible. Differential Revision: http://reviews.llvm.org/D14081 llvm-svn: 251390
* Convert cost table lookup functions to return a pointer to the entry or ↵Craig Topper2015-10-273-149/+114
| | | | | | | | | | nullptr instead of the index. This avoid mentioning the table name an extra time and allows the lookup to be done directly in the ifs by relying on the bool conversion of the pointer. While there make use of ArrayRef and std::find_if. llvm-svn: 251382
* [x86] replace integer logic ops with packed SSE FP logic opsSanjay Patel2015-10-271-2/+26
| | | | | | | | | | | | | | | | | | | If we have an operand to a bitwise logic op that's already in an XMM register and the result is going to be sent to an XMM register, then use an SSE logic op to avoid moves between the integer and vector register files. Related commits: http://reviews.llvm.org/rL248395 http://reviews.llvm.org/rL248399 http://reviews.llvm.org/rL248404 http://reviews.llvm.org/rL248409 http://reviews.llvm.org/rL248415 This should solve PR22428: https://llvm.org/bugs/show_bug.cgi?id=22428 llvm-svn: 251378
* [mips][ias] Fold needsExpansion() and expandInstruction() together. NFC.Daniel Sanders2015-10-261-122/+83
| | | | | | | | | | | | | | Summary: Previously we maintained two separate switch statements that had to be kept in sync. This patch merges them into a single switch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14012 llvm-svn: 251369
* reorganize logic; NFCI (retry r251349)Sanjay Patel2015-10-261-13/+13
| | | | | | | | | This is a preliminary step before adding another optimization to PerformBITCASTCombine(). ..and I really hope it's NFC this time! llvm-svn: 251357
* ARM: make sure VFP loads and stores are properly aligned.Tim Northover2015-10-261-10/+12
| | | | | | | Both VLDRS and VLDRD fault if the memory is not 4 byte aligned, which wasn't really being checked before, leading to faults at runtime. llvm-svn: 251352
* revert r251349; it included code for a functional changeSanjay Patel2015-10-261-33/+14
| | | | llvm-svn: 251350
* reorganize logic; NFCISanjay Patel2015-10-261-14/+33
| | | | | | | This is a preliminary step before adding another optimization to PerformBITCASTCombine(). llvm-svn: 251349
* ARM/ELF: Restore original (pre-r251322) logic for deciding whether to use GOT.Peter Collingbourne2015-10-262-2/+2
| | | | | | | Unbreaks linking with gold, which cannot resolve direct relocations referring to global symbols. llvm-svn: 251342
* [safestack] Fast access to the unsafe stack pointer on AArch64/Android.Evgeniy Stepanov2015-10-264-9/+31
| | | | | | | | | | | | | | | | | | | | | Android libc provides a fixed TLS slot for the unsafe stack pointer, and this change implements direct access to that slot on AArch64 via __builtin_thread_pointer() + offset. This change also moves more code into TargetLowering and its target-specific subclasses to get rid of target-specific codegen in SafeStackPass. This change does not touch the ARM backend because ARM lowers builting_thread_pointer as aeabi_read_tp, which is not available on Android. The previous iteration of this change was reverted in r250461. This version leaves the generic, compiler-rt based implementation in SafeStack.cpp instead of moving it to TargetLoweringBase in order to allow testing without a TargetMachine. llvm-svn: 251324
* ARM/ELF: Better codegen for global variable addresses.Peter Collingbourne2015-10-2613-168/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In PIC mode we were previously computing global variable addresses (or GOT entry addresses) by adding the PC, the PC-relative GOT displacement and the GOT-relative symbol/GOT entry displacement. Because the latter two displacements are fixed, we ended up performing one more addition than necessary. This change causes us to compute addresses using a single PC-relative displacement, resulting in a shorter code sequence. This reduces code size by about 4% in a recent build of Chromium for Android. As a result of this change we no longer need to compute the GOT base address in the ARM backend, which allows us to remove the Global Base Reg pass and SDAG lowering for the GOT. We also now no longer use the GOT when addressing a symbol which is known to be defined in the same linkage unit. Specifically, the symbol must have either hidden visibility or a strong definition in the current module in order to not use the the GOT. This is a change from the previous behaviour where we would use the GOT to address externally visible symbols defined in the same module. I think the only cases where this could matter are cases involving symbol interposition, but we don't really support that well anyway. Differential Revision: http://reviews.llvm.org/D13650 llvm-svn: 251322
* [SystemZ] LTGFR use regclass should be GR32, not GR64.Jonas Paulsson2015-10-261-1/+1
| | | | | | | Discovered by testing int-cmp-44.ll with -verify-machineinstrs (added to test run). llvm-svn: 251299
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