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* Add support to the ARM MC infrastructure to support mcr and friends. This ↵Owen Anderson2011-01-134-29/+225
| | | | | | | | | | | | | | requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
* Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen2011-01-1312-24/+26
| | | | llvm-svn: 123399
* Tidy comments, indentation, and 80-column violations.Bob Wilson2011-01-131-37/+39
| | | | llvm-svn: 123397
* Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target andKevin Enderby2011-01-131-2/+4
| | | | | | directional local labels like 1f and 2b. llvm-svn: 123393
* When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctlyJim Grosbach2011-01-131-4/+7
| | | | | | | | | set up the source operands. The original instr has an immediate operand that should be replaced with the frame reg operand rather than just adding the reg operand. Previously, the instruction ended up with too many operands causing an assert() when adding the default predicate. rdar://8825456 llvm-svn: 123387
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-139-75/+219
| | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
* Experiment with changing the default 32-bit linux stack alignment toEric Christopher2011-01-131-3/+3
| | | | | | 16 bytes for PR8969. Update all testcases accordingly. llvm-svn: 123367
* Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 orKevin Enderby2011-01-131-2/+12
| | | | | | | | .code 32 if the TargetMachine's isThumb() boolean does not match. The correct fix is to switch ARM subtargets at that point and is tracked by rdar://8856789 which is bigger task. llvm-svn: 123353
* Change call to Error() to assert()Jason W Kim2011-01-131-4/+1
| | | | llvm-svn: 123350
* Added clarifying commentJason W Kim2011-01-121-0/+2
| | | | llvm-svn: 123341
* JimG sez: "The value-kinds look like masks, but they're not consistently usedJason W Kim2011-01-121-2/+2
| | | | | | | | | | | that way, unfortunately. If you want to change them to work additively instead of a one-variant-kind-per-symbolref, that's great and I completely agree it's worth doing, but it really should be a separate patch. Until then, this isn't correct." So I am reverting this bit until a more opportune time. llvm-svn: 123340
* Sort the register list based on the *actual* register numbers rather than theBill Wendling2011-01-121-5/+5
| | | | | | enum values we give to them. <rdar://problem/8823730> llvm-svn: 123321
* Mostly undo r123297, but move the default case in EvaluateAsPCRel to the topMatt Beaumont-Gay2011-01-121-3/+3
| | | | | | of the switch block to appease GCC. llvm-svn: 123317
* Add another note taken from the gcc bugzilla.Nick Lewycky2011-01-121-1/+20
| | | | llvm-svn: 123315
* Implement RETURNADDR and FRAMEADDR lowering in SPARC backend.Venkatraman Govindaraju2011-01-123-4/+85
| | | | llvm-svn: 123310
* Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to Venkatraman Govindaraju2011-01-122-3/+5
| | | | | | ensure %o7 is not assigned as the destination of getpcx instruction. llvm-svn: 123304
* Fix SPARC backend call instruction so that arguments passed through registersVenkatraman Govindaraju2011-01-122-11/+24
| | | | | | | are correctly marked as used instead of passing all possible argument registers as used. llvm-svn: 123301
* Prefer llvm_unreachable to assert(0)Matt Beaumont-Gay2011-01-121-3/+3
| | | | llvm-svn: 123297
* 1. Support ELF pcrel relocations for movw/movt:Jason W Kim2011-01-124-5/+49
| | | | | | | | R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) llvm-svn: 123294
* Workaround for bug 8721.Jason W Kim2011-01-111-0/+106
| | | | | | .s Test added. llvm-svn: 123292
* SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CCVenkatraman Govindaraju2011-01-111-15/+19
| | | | llvm-svn: 123281
* Clean up ARM subtarget code by using Triple ADT.Evan Cheng2011-01-116-13/+15
| | | | llvm-svn: 123276
* McARM: Fill in GetMnemonicAcceptInfo().Daniel Dunbar2011-01-111-2/+17
| | | | llvm-svn: 123253
* Fix a comment: We now have intrinsics for vcvtr.Bob Wilson2011-01-111-1/+0
| | | | llvm-svn: 123246
* Fix PR8946, a missing reg/reg form of movdqu.Chris Lattner2011-01-111-0/+4
| | | | llvm-svn: 123242
* McARM: Sketch some logic for determining when to add carry set and ↵Daniel Dunbar2011-01-111-4/+48
| | | | | | predication code operands based on the "canonical mnemonic". llvm-svn: 123239
* McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out theDaniel Dunbar2011-01-111-11/+32
| | | | | | | | | | carry setting flag from the mnemonic. Note that this currently involves me disabling a number of working cases in arm_instructions.s, this is a hopefully short term evil which will be rapidly fixed (and greatly surpassed), assuming my current approach flies. llvm-svn: 123238
* Fix a thinko in 123226 that caused test failures on "other" platforms.Kalle Raiskila2011-01-111-1/+1
| | | | llvm-svn: 123229
* Add a "nop filler" pass to SPU.Kalle Raiskila2011-01-116-1/+166
| | | | | | | | | | | | | | | Filling no-ops is done just before emitting of assembly, when the instruction stream is final. No-ops are inserted to align the instructions so the dual-issue of the pipeline is utilized. This speeds up generated code with a minimum of 1% on a select set of algorithms. This pass may be redundant if the instruction scheduler and all subsequent passes that modify the instruction stream (prolog+epilog inserter, register scavenger, are there others?) are made aware of the instruction alignments. llvm-svn: 123226
* Teach constant folding to perform conversions from constant floatingChandler Carruth2011-01-111-55/+0
| | | | | | | | point values to their integer representation through the SSE intrinsic calls. This is the last part of a README.txt entry for which I have real world examples. llvm-svn: 123206
* Fix a random missed optimization by making InstCombine more aggressive when ↵Owen Anderson2011-01-111-15/+0
| | | | | | | | determining which bits are demanded by a comparison against a constant. llvm-svn: 123203
* Even if we don't have 7 bytes of stack space we may need to save andEric Christopher2011-01-111-1/+8
| | | | | | | | restore the stack pointer from the frame pointer on thumbv6. Fixes rdar://8819685 llvm-svn: 123196
* Expand on the safeness of restoring the sp from the fp a bit more.Eric Christopher2011-01-101-1/+2
| | | | llvm-svn: 123193
* +0.0 vs -0.0 differences can be handled by looking at the user of theChris Lattner2011-01-101-3/+19
| | | | | | operation in some cases. llvm-svn: 123190
* McARM: Flush out hard coded known non-predicated mnemonic list.Daniel Dunbar2011-01-101-3/+12
| | | | llvm-svn: 123189
* McARM: Mark some T2 ...s instructions as codegen only, they aren't realDaniel Dunbar2011-01-101-4/+4
| | | | | | instructions but are restricted pseudo forms. llvm-svn: 123177
* ARM/MC: Mark several '...S' instructions as codegen only, they aren't realDaniel Dunbar2011-01-101-4/+6
| | | | | | instructions but are restricted pseudo forms. llvm-svn: 123176
* MC/ARM/AsmParser: Minor nitty fixes.Daniel Dunbar2011-01-101-3/+3
| | | | llvm-svn: 123175
* Fix merge falloutAnton Korobeynikov2011-01-101-2/+2
| | | | llvm-svn: 123172
* Update CMake stuffAnton Korobeynikov2011-01-1014-16/+15
| | | | llvm-svn: 123171
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-1089-476/+500
| | | | | | and fixes here and there. llvm-svn: 123170
* MC/ARM/AsmParser: Split out SplitMnemonicAndCC().Daniel Dunbar2011-01-101-17/+29
| | | | llvm-svn: 123169
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-104-5/+4
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* expand on a noteChris Lattner2011-01-101-4/+9
| | | | llvm-svn: 123145
* typoChris Lattner2011-01-091-1/+1
| | | | llvm-svn: 123142
* xref a PR #Chris Lattner2011-01-091-22/+2
| | | | llvm-svn: 123141
* Add a note about the inability to model FP -> int conversions whichChandler Carruth2011-01-091-0/+55
| | | | | | | | perform rounding other than truncation in the IR. Common C code for this turns into really an LLVM intrinsic call that blocks a lot of further optimizations. llvm-svn: 123135
* Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual andJakob Stoklund Olesen2011-01-091-1/+3
| | | | | | | | | | | | | physical register numbers. This makes the hack used in LiveInterval official, and lets LiveInterval be oblivious of stack slots. The isPhysicalRegister() and isVirtualRegister() predicates don't know about this, so when a variable may contain a stack slot, isStackSlot() should always be tested first. llvm-svn: 123128
* Add a note about a missed FP optimization.Chandler Carruth2011-01-091-0/+24
| | | | llvm-svn: 123126
* Another missed memset in std::vector initialization.Chandler Carruth2011-01-091-0/+19
| | | | llvm-svn: 123116
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