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* CostModel: Add tables for the common x86 compares.Nadav Rotem2012-11-052-8/+83
| | | | llvm-svn: 167421
* Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation.Nadav Rotem2012-11-051-3/+10
| | | | llvm-svn: 167412
* Suppress signed/unsigned comparison warning.Richard Smith2012-11-051-2/+2
| | | | llvm-svn: 167410
* Cost Model: Normalize the insert/extract index when splitting typesNadav Rotem2012-11-051-3/+20
| | | | llvm-svn: 167402
* Cost Model: teach the cost model about expanding integers.Nadav Rotem2012-11-051-2/+3
| | | | llvm-svn: 167401
* On PowerPC64, integer return values (as well as arguments) are supposedUlrich Weigand2012-11-052-7/+50
| | | | | | | | | | | | | | | | | | | | | | | | | to be extended to a full register. This is modeled in the IR by marking the return value (or argument) with a signext or zeroext attribute. However, while these attributes are respected for function arguments, they are currently ignored for function return values by the PowerPC back-end. This patch updates PPCCallingConv.td to ask for the promotion to i64, and fixes LowerReturn and LowerCallResult to implement it. The new test case verifies that both arguments and return values are properly extended when passing them; and also that the optimizers understand incoming argument and return values are in fact guaranteed by the ABI to be extended. The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll, since the test case used a "ret" instruction to create a use of an i32 value at the end of the function (to set up data flow as required for what the test is intended to test). Since there's now an implicit promotion to i64, that data flow no longer works as expected. To fix this, this patch now adds an extra "add" to ensure we have an appropriate use of the i32 value. llvm-svn: 167396
* Implement the cost of abnormal x86 instruction lowering as a table.Nadav Rotem2012-11-052-58/+46
| | | | llvm-svn: 167395
* Add support for the PowerPC-specific inline asm Z constraint and y modifier.Hal Finkel2012-11-052-2/+27
| | | | | | | | | | The Z constraint specifies an r+r memory address, and the y modifier expands to the "r, r" in the asm string. For this initial implementation, the base register is forced to r0 (which has the special meaning of 0 for r+r addressing on PowerPC) and the full address is taken in the second register. In the future, this should be improved. llvm-svn: 167388
* [PATCH] PowerPC: Expand load extend vector operationsAdhemerval Zanella2012-11-051-0/+10
| | | | | | | This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for vector types when altivec is enabled. llvm-svn: 167386
* Remove alignments from folding tables for scalar FMA4 instructions.Craig Topper2012-11-041-16/+16
| | | | llvm-svn: 167366
* [mips] Set flag neverHasSideEffects flag on floating point conversionAkira Hatanaka2012-11-032-6/+11
| | | | | | instructions. llvm-svn: 167348
* X86 CostModel: Add support for a some of the common arithmetic instructions ↵Nadav Rotem2012-11-032-6/+73
| | | | | | for SSE4, AVX and AVX2. llvm-svn: 167347
* [mips] Set flag isAsCheapAsAMove flag on instruction LUi.Akira Hatanaka2012-11-031-1/+1
| | | | llvm-svn: 167345
* [mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka2012-11-035-13/+47
| | | | | | register is needed. llvm-svn: 167341
* [mips] Do not reserve all 64-bit registers, but only the ones which need to beAkira Hatanaka2012-11-021-8/+4
| | | | | | | reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly returns an empty set of integer registers. llvm-svn: 167335
* Add a stub for the x86 cost model impl. Implement a basic cost rule for ↵Nadav Rotem2012-11-022-2/+18
| | | | | | inserting/extracting from XMM registers. llvm-svn: 167333
* Scalar Bitcasts and Truncs are usually freeNadav Rotem2012-11-021-0/+5
| | | | llvm-svn: 167323
* Vext Lowering was missing opportunitiesQuentin Colombet2012-11-021-4/+40
| | | | llvm-svn: 167318
* [mips] Use register number instead of name to print register $AT.Akira Hatanaka2012-11-021-2/+2
| | | | llvm-svn: 167315
* [mips] Add function MipsFrameLowering::estimateStackSize.Akira Hatanaka2012-11-022-0/+37
| | | | | | | This function estimates stack size and will be called before PrologEpilogInserter scans the callee-saved registers. llvm-svn: 167313
* [mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the sizeAkira Hatanaka2012-11-022-0/+7
| | | | | | of the incoming argument area. llvm-svn: 167312
* [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directiveAkira Hatanaka2012-11-025-16/+3
| | | | | | | "set .noat" so that the assembler doesn't issue warnings when register $AT is used. llvm-svn: 167310
* Use the relationship models infrastructure to add two relations - getPredOpcodePranav Bhandarkar2012-11-013-211/+139
| | | | | | | | | | and getPredNewOpcode. The first relates non predicated instructions with their predicated forms and the second relates predicated instructions with their predicate-new forms. Patch by Jyotsna Verma! llvm-svn: 167243
* Revert the majority of the next patch in the address space series:Chandler Carruth2012-11-016-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r165941: Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis. Despite this commit log, this change primarily changed stuff outside of VMCore, and those changes do not carry any tests for correctness (or even plausibility), and we have consistently found questionable or flat out incorrect cases in these changes. Most of them are probably correct, but we need to devise a system that makes it more clear when we have handled the address space concerns correctly, and ideally each pass that gets updated would receive an accompanying test case that exercises that pass specificaly w.r.t. alternate address spaces. However, from this commit, I have retained the new C API entry points. Those were an orthogonal change that probably should have been split apart, but they seem entirely good. In several places the changes were very obvious cleanups with no actual multiple address space code added; these I have not reverted when I spotted them. In a few other places there were merge conflicts due to a cleaner solution being implemented later, often not using address spaces at all. In those cases, I've preserved the new code which isn't address space dependent. This is part of my ongoing effort to clean out the partial address space code which carries high risk and low test coverage, and not likely to be finished before the 3.2 release looms closer. Duncan and I would both like to see the above issues addressed before we return to these changes. llvm-svn: 167222
* Revert the series of commits starting with r166578 which introduced theChandler Carruth2012-11-017-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getIntPtrType support for multiple address spaces via a pointer type, and also introduced a crasher bug in the constant folder reported in PR14233. These commits also contained several problems that should really be addressed before they are re-committed. I have avoided reverting various cleanups to the DataLayout APIs that are reasonable to have moving forward in order to reduce the amount of churn, and minimize the number of commits that were reverted. I've also manually updated merge conflicts and manually arranged for the getIntPtrType function to stay in DataLayout and to be defined in a plausible way after this revert. Thanks to Duncan for working through this exact strategy with me, and Nick Lewycky for tracking down the really annoying crasher this triggered. (Test case to follow in its own commit.) After discussing with Duncan extensively, and based on a note from Micah, I'm going to continue to back out some more of the more problematic patches in this series in order to ensure we go into the LLVM 3.2 branch with a reasonable story here. I'll send a note to llvmdev explaining what's going on and why. Summary of reverted revisions: r166634: Fix a compiler warning with an unused variable. r166607: Add some cleanup to the DataLayout changes requested by Chandler. r166596: Revert "Back out r166591, not sure why this made it through since I cancelled the command. Bleh, sorry about this! r166591: Delete a directory that wasn't supposed to be checked in yet. r166578: Add in support for getIntPtrType to get the pointer type based on the address space. llvm-svn: 167221
* Cleanup another place redundant SP maintainedMichael Liao2012-11-011-4/+4
| | | | llvm-svn: 167209
* (For X86) Enhancement to add-carray/sub-borrow (adc/sbb) optimization.Shuxin Yang2012-10-311-4/+29
| | | | | | | | | | | | The adc/sbb optimization is to able to convert following expression into a single adc/sbb instruction: (ult) ... = x + 1 // where the ult is unsigned-less-than comparison (ult) ... = x - 1 This change is to flip the "x >u y" (i.e. ugt comparison) in order to expose the adc/sbb opportunity. llvm-svn: 167180
* Fix a bug in the cost calculation of vector casts. Detect situations where ↵Nadav Rotem2012-10-311-26/+41
| | | | | | bitcasts cost zero. llvm-svn: 167170
* [mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enablesAkira Hatanaka2012-10-312-2/+7
| | | | | | re-materialization of immediate loads. llvm-svn: 167153
* Implement ADJCALLSTACKUP and ADJCALLSTACKDOWNReed Kotler2012-10-316-9/+67
| | | | llvm-svn: 167107
* Add scalar forms of FMA4 VFNMSUB/VFNMADD to folding tables. Patch from ↵Craig Topper2012-10-311-0/+8
| | | | | | Cameron McInally. llvm-svn: 167106
* Clean up redundant SP register maintained in X86 TLIMichael Liao2012-10-312-12/+7
| | | | llvm-svn: 167104
* This patch addresses an ABI compatibility issue with empty aggregateBill Schmidt2012-10-311-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | parameters. Examples of these are: struct { } a; union { } b[256]; int a[0]; An empty aggregate has an address, although dereferencing that address is pointless. When passed as a parameter, an empty aggregate does not consume a protocol register, nor does it consume a doubleword in the parameter save area. Passing an empty aggregate by reference passes an address just as for any other aggregate. Returning an empty aggregate uses GPR3 as a hidden address of the return value location, just as for any other aggregate. The patch modifies PPCTargetLowering::LowerFormalArguments_64SVR4 and PPCTargetLowering::LowerCall_64SVR4 to properly skip empty aggregate parameters passed by value. The handling of return values and by-reference parameters was already correct. Built on powerpc64-unknown-linux-gnu and tested with no new regressions. A test case is included to test proper handling of empty aggregate parameters on both sides of the function call protocol. llvm-svn: 167090
* X86 SSE: update rsqrtss and rcpss to use two source operands andManman Ren2012-10-301-4/+39
| | | | | | | | | | | | the first source operand is tied to the destination operand. This is to accurately model the corresponding instructions where the upper bits are unmodified. rdar://12558838 PR14221 llvm-svn: 167064
* X86 MMX: optimize transfer from mmx to i32Manman Ren2012-10-303-2/+20
| | | | | | | | | We used to generate a store (movq) + a load. Now we use movd. rdar://9946746 llvm-svn: 167056
* [mips] Allow tail-call optimization for vararg functions and functions whichAkira Hatanaka2012-10-302-15/+20
| | | | | | use the caller's stack. llvm-svn: 167048
* Add code for saving formal argument information to MipsFunctionInfo. ThisAkira Hatanaka2012-10-302-0/+13
| | | | | | | information will be used by IsEligibleForTailCallOptimization to determine whether a call can be tail-call optimized. llvm-svn: 167043
* Add definition of function MipsTargetLowering::passArgOnStack which emits nodesAkira Hatanaka2012-10-302-0/+22
| | | | | | for passing a function call argument on a stack. llvm-svn: 167041
* Do not do tail-call optimization if target is mips16.Akira Hatanaka2012-10-301-0/+4
| | | | llvm-svn: 167039
* PowerPC: Expand FSRQT for vector typesAdhemerval Zanella2012-10-301-0/+6
| | | | | | | This patch expands FSQRT for floating point vector types when altivec is used. llvm-svn: 167034
* Enable ELF machine type to be specified explicitly in X86 backendMichael Liao2012-10-303-15/+19
| | | | llvm-svn: 167027
* Change ForceSizeOpt attribute into MinSize attributeQuentin Colombet2012-10-302-4/+5
| | | | llvm-svn: 167020
* PowerPC: More support for Altivec compare operationsAdhemerval Zanella2012-10-302-13/+141
| | | | | | | | This patch adds more support for vector type comparisons using altivec. It adds correct support for v16i8, v8i16, v4i32, and v4f32 vector types for comparison operators ==, !=, >, >=, <, and <=. llvm-svn: 167015
* Use TargetTransformInfo to control switch-to-lookup table transformationHans Wennborg2012-10-301-1/+6
| | | | | | | | | | | | | | When the switch-to-lookup tables transform landed in SimplifyCFG, it was pointed out that this could be inappropriate for some targets. Since there was no way at the time for the pass to know anything about the target, an awkward reverse-transform was added in CodeGenPrepare that turned lookup tables back into switches for some targets. This patch uses the new TargetTransformInfo to determine if a switch should be transformed, and removes CodeGenPrepare::ConvertLoadToSwitch. llvm-svn: 167011
* Remove an invalid assert in TargetTransformImplHal Finkel2012-10-301-4/+13
| | | | | | | getCastInstrCost had an assert prohibiting scalar to vector casts. Such casts, however, are allowed. This should make the vectorizer buildbot happier. llvm-svn: 166998
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-304-4/+6
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Change mips16 delay slot jumps to non delay slot forms by default.Reed Kotler2012-10-302-3/+10
| | | | | | | | We will make them delay slot forms if there is something that can be placed in the delay slot during a separate pass. Mips16 extended instructions cannot be placed in delay slots. llvm-svn: 166990
* Re-commit r166971. I reverted it to quickly, when buildbots didn't have a chanceJakub Staszak2012-10-301-4/+4
| | | | | | to test it with chapni's fix (-mattr=+avx). llvm-svn: 166985
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-292-11/+23
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Revert r166971. It causes buildbot failure. To be investigated.Jakub Staszak2012-10-291-4/+4
| | | | llvm-svn: 166979
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