summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Remove the separate explicit AES instruction patterns. They are equivalent ↵Craig Topper2011-12-291-48/+5
| | | | | | to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. llvm-svn: 147342
* Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled ↵Craig Topper2011-12-291-3/+2
| | | | | | on its own without disabling SSE4.2 or SSE4A. llvm-svn: 147339
* Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL ↵Craig Topper2011-12-291-9/+8
| | | | | | for v16i16 and v32i8. llvm-svn: 147337
* Remove some elses after returns.Craig Topper2011-12-291-7/+10
| | | | llvm-svn: 147336
* Remove trailing spaces. Fix an assert to use && instead of || before string. ↵Craig Topper2011-12-291-7/+5
| | | | | | Add same assert on similar code path. llvm-svn: 147335
* Fix type-checking for load transformation which is not legal on ↵Eli Friedman2011-12-281-1/+2
| | | | | | floating-point types. PR11674. llvm-svn: 147323
* Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.Elena Demikhovsky2011-12-281-4/+25
| | | | | | | Matching MOVLP mask for AVX (265-bit vectors) was wrong. The failure was detected by conformance tests. llvm-svn: 147308
* Clean up some Release build warnings.Benjamin Kramer2011-12-274-24/+16
| | | | llvm-svn: 147289
* Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for ↵Craig Topper2011-12-271-1/+6
| | | | | | consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. llvm-svn: 147287
* Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks.Venkatraman Govindaraju2011-12-253-1/+28
| | | | llvm-svn: 147269
* Section relative fixups are a coff concept, not a x86 one. Replace theRafael Espindola2011-12-243-6/+6
| | | | | | x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4. llvm-svn: 147252
* Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when theChandler Carruth2011-12-241-18/+14
| | | | | | | | | | | | | | | | | | LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] llvm-svn: 147251
* Add systematic testing for cttz as well, and fix the bug I spotted byChandler Carruth2011-12-241-1/+2
| | | | | | inspection earlier. llvm-svn: 147250
* Chandler fixed this.Benjamin Kramer2011-12-241-32/+0
| | | | llvm-svn: 147247
* Expand more when we have a nice 'tzcnt' instruction, to avoid generatingChandler Carruth2011-12-241-0/+4
| | | | | | | | | | | 'bsf' instructions here. This one is actually debatable to my eyes. It's not clear that any chip implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding. Still, this restores the old behavior with 'tzcnt' enabled for now. llvm-svn: 147246
* Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to theChandler Carruth2011-12-243-11/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | X86ISelLowering C++ code. Because this is lowered via an xor wrapped around a bsr, we want the dagcombine which runs after isel lowering to have a chance to clean things up. In particular, it is very common to see code which looks like: (sizeof(x)*8 - 1) ^ __builtin_clz(x) Which is trying to compute the most significant bit of 'x'. That's actually the value computed directly by the 'bsr' instruction, but if we match it too late, we'll get completely redundant xor instructions. The more naive code for the above (subtracting rather than using an xor) still isn't handled correctly due to the dagcombine getting confused. Also, while here fix an issue spotted by inspection: we should have been expanding the zero-undef variants to the normal variants when there is an 'lzcnt' instruction. Do so, and test for this. We don't want to generate unnecessary 'bsr' instructions. These two changes fix some regressions in encoding and decoding benchmarks. However, there is still a *lot* to be improve on in this type of code. llvm-svn: 147244
* Fix Comments.Jakob Stoklund Olesen2011-12-241-3/+3
| | | | llvm-svn: 147238
* Add MachineMemOperands to instructions generated in storeRegToStackSlot orAkira Hatanaka2011-12-241-2/+16
| | | | | | loadRegFromStackSlot. llvm-svn: 147235
* Detect unaligned loads/stores that have been added for Mips64 support.Akira Hatanaka2011-12-241-1/+8
| | | | llvm-svn: 147234
* If target ABI is N64, LEA should be daddiu.Akira Hatanaka2011-12-241-1/+1
| | | | llvm-svn: 147232
* Move x86 specific bits of the COFF writer to lib/Target/X86.Rafael Espindola2011-12-244-1/+74
| | | | llvm-svn: 147231
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-233-13/+377
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. llvm-svn: 147211
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-224-7/+23
| | | | | | | | | | | My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. llvm-svn: 147204
* Fix 80-column violations.Chad Rosier2011-12-221-11/+14
| | | | llvm-svn: 147192
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-224-16/+70
| | | | | | rdar://10558523 llvm-svn: 147189
* Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.Bob Wilson2011-12-221-1/+1
| | | | | | Noticed by inspection; I don't have a testcase for this. llvm-svn: 147188
* Tidy up. Use predicate function a bit more liberally.Jim Grosbach2011-12-221-97/+52
| | | | llvm-svn: 147184
* Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola2011-12-221-8/+1
| | | | | | Fixes PR11214. llvm-svn: 147180
* ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.Jim Grosbach2011-12-221-0/+3
| | | | | | | | | | The value from the operands isn't right yet, but we weren't encoding it at all previously. The parser needs to twiddle the values when building the instruction. Partial for: rdar://10558523 llvm-svn: 147170
* Remove some bogus comments.Jim Grosbach2011-12-221-36/+18
| | | | llvm-svn: 147169
* ARM pre-UAL aliases. fcmp[sd].Jim Grosbach2011-12-222-1/+3
| | | | llvm-svn: 147158
* Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for ↵Rafael Espindola2011-12-222-15/+3
| | | | | | | | reporting it. It does need some some tests... llvm-svn: 147154
* ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach2011-12-221-0/+33
| | | | | | | | Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 llvm-svn: 147153
* ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.Jim Grosbach2011-12-221-0/+4
| | | | llvm-svn: 147152
* Tidy up. Trailing whitespace.Jim Grosbach2011-12-221-2/+2
| | | | llvm-svn: 147151
* Nuke invalid comment from copy/paste.Jim Grosbach2011-12-221-1/+0
| | | | llvm-svn: 147150
* Move the Mips only bits of the ELF writer to lib/Target/Mips.Rafael Espindola2011-12-224-21/+145
| | | | llvm-svn: 147133
* Make the virtual methods in ARMELFObjectWriter public.Rafael Espindola2011-12-221-7/+6
| | | | llvm-svn: 147132
* Move the MBlaze ELF writer bits to lib/Target/MBlaze.Rafael Espindola2011-12-224-9/+85
| | | | llvm-svn: 147129
* Fix cmake.Rafael Espindola2011-12-221-0/+1
| | | | llvm-svn: 147126
* Move PPC bits to lib/Target/PowerPC.Rafael Espindola2011-12-222-1/+112
| | | | llvm-svn: 147124
* Hopefully fix the cmake build.Rafael Espindola2011-12-221-0/+1
| | | | llvm-svn: 147121
* Fix name in comments.Rafael Espindola2011-12-221-1/+1
| | | | llvm-svn: 147119
* Local dynamic TLS model for direct object output. Create the correct TLS MIPSAkira Hatanaka2011-12-223-0/+22
| | | | | | | | ELF relocations. Patch by Jack Carter. llvm-svn: 147118
* Unbreak cmake build after r147115.Richard Smith2011-12-221-0/+1
| | | | llvm-svn: 147117
* Move the ARM specific parts of the ELF writer to Target/ARM.Rafael Espindola2011-12-223-2/+291
| | | | llvm-svn: 147115
* ARM NEON mnemonic aliase for vrecpeq.Jim Grosbach2011-12-211-0/+3
| | | | llvm-svn: 147109
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-211-3/+11
| | | | llvm-svn: 147104
* ARM NEON optional data type on VSWP instructions.Jim Grosbach2011-12-211-0/+6
| | | | llvm-svn: 147103
* ARM NEON mnemonic aliases for vzipq and vswpq.Jim Grosbach2011-12-211-0/+3
| | | | llvm-svn: 147102
OpenPOWER on IntegriCloud